[Coco] Last video I promise... :)

[Luis Antoniosi (CoCoDemus)]

Well not at the limit but the timing quest complains about very long
combinatorial paths but it's not easy to make them shorter. Lots of
processing is done to be able to do artifacting and shrinking.

I have checked the input/output timings, slack time, path times, in fact
that is a lot to learn on the timing quest analyzer. I had to set false
paths between few  pins, essentially the clock input pin and the DRAM CLK
output.

Today I saw there are difference in timings among different pins ? The blue
input pin shows longer setup times. Should I change it to another pin, to
be in pair with red/green ?


Luis Felipe Antoniosi



On Fri, Dec 5, 2014 at 5:37 PM, Mark McDougall <msmcdoug at iinet.net.au>
wrote:

> On 6/12/2014 3:09 AM, Luis Antoniosi (CoCoDemus) wrote:
>
>  This is not external interference, it's merely slack time that is
>> affecting
>> how the colors are digitized. Let's say: the altera is running the code at
>> the limit of it's speed. This cause the code to get out of sync with the
>> clock and then, the color is digitized in the wrong level of the DAC, or
>> it
>> didn't have time enough for the differential to change its value. Solving
>> this is much more difficult.
>>
>
> What basis do you have to suggest that it is running "at the limit of its
> speed"? Have you looked at the output of the timing analyzer? Do you
> understand it? If not, I suggest you read up on it. It is important.
>
> For that matter, have you set the proper timing constraints on the ADC
> inputs and the DAC outputs? If you haven't, then you are very likely
> sampling (and outputting) different channels at different points in time,
> resulting in bad colours.
>
>
> Regards,
>
> --
> |              Mark McDougall                | "Electrical Engineers do it
> |  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"
>
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