[Coco] Last video I promise... :)

[Mark McDougall]

On 6/12/2014 9:57 AM, Luis Antoniosi (CoCoDemus) wrote:

> Well not at the limit but the timing quest complains about very long
> combinatorial paths but it's not easy to make them shorter. Lots of
> processing is done to be able to do artifacting and shrinking.

That's when you need to start pipeling the operations. Otherwise you're not 
going to get good results.

> I have checked the input/output timings, slack time, path times, in fact
> that is a lot to learn on the timing quest analyzer. I had to set false
> paths between few  pins, essentially the clock input pin and the DRAM CLK
> output.

Yes, which is why a lot of people doing homebrew FPGA don't bother and hope 
for the best!

> Today I saw there are difference in timings among different pins ? The blue
> input pin shows longer setup times. Should I change it to another pin, to
> be in pair with red/green ?

No, don't change pins. Use timing constraints on each to bring them into 
line. For both input and output.

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"