[Coco] deuce memory bandwidth?

[jdaggett at gate.net]

Kevin

The Coco's all used interleaved DMA for cpu  and video time. The 
video uses the first half of the machine cycle (Eclk low) and the 
CPU acesses memory and peripheral during the second half of the 
machine cycle (Eclk high). The GIME chip and the MC6847 all align 
video timing off of the buss clock. Also why  part of the reason for 
the odd ball clock frequency. 

For the Coco 1/2 the crystal frequency divided by 4 is the color b 
urst frequency. From there generatign the two phase E and Q 
clocks does another divide by four. This yields the common 0.894 
MHz buss speed. High speed is derived by dividing the crystal by 2. 
For the Coco3 the GIME chip divided the 28.6 MHz crystal by 8 to 
get color burst and by 4 to get twice the color burst. this feeds the 
phase generator and the two familiar E and Q clock frequencies for 
the 6809E. 

The 6809 chip itself has its own crystal oscillator and phase 
generator inside. The crystal itself must run at 4 times the buss 
frequency. The same scheme is used on the HC11 and HC12 
microcontrollers. 


james


On 7 Aug 2004 at 9:22, Kevin Diggs wrote:

Date sent:      	Sat, 07 Aug 2004 09:22:49 -0700
From:           	Kevin Diggs <kevdig at hypersurf.com>
To:             	coco at maltedmedia.com
Subject:        	[Coco] deuce memory bandwidth?
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> Hi,
> 
>  Anyone know what the memory bandwidth for the deuce is? Is
> it one byte per two cycles (cycle == 1.78 MHz?)? If this is correct it
> would make single cycle instructions kinda useless without an
> instruction cache, right?
> 
>      kevin
> 
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