[Coco] deuce memory bandwidth?

[jdaggett at gate.net]

Kevin 

one other note. 

The 6809/6309 operate under a two phase clock system. The two 
clocks are in quadrature and the Q clock leads the E clock by 90 
degress.  All machine cycles are referenced to the falling edge of 
the E clock. 

The CPU latches data out on databuss on the rising edge of the E 
clock and latches data into the core from the data buss on the 
falling edge of the E clock. Data  being read by the CPU must be 
stable by the falling edge of the Eclock and should  have a hold 
time of about 5% of the machine cycle after the fall of the Eclock. 
One more item, the address bus is valid on the falling edge of the Q 
clock. 

By using a two phase clock the 6809 can move stuff around withing 
the processor four times faster than a CISC processor usign a 
single pahse clock. If you XOR the two phase clocks, you get an 
equivalent 4 times frequency clock. 


james


On 7 Aug 2004 at 9:22, Kevin Diggs wrote:

Date sent:      	Sat, 07 Aug 2004 09:22:49 -0700
From:           	Kevin Diggs <kevdig at hypersurf.com>
To:             	coco at maltedmedia.com
Subject:        	[Coco] deuce memory bandwidth?
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> Hi,
> 
>  Anyone know what the memory bandwidth for the deuce is? Is
> it one byte per two cycles (cycle == 1.78 MHz?)? If this is correct it
> would make single cycle instructions kinda useless without an
> instruction cache, right?
> 
>      kevin
> 
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