[Coco] A Video Timing Question

[tim franklinlabs.com]

   From what I'm reading, it sounds like there's no "This is how you do
   it" method and there are several approaches. My FIFO method is similar
   to what you're speaking of Mark in that I allow the CPU to write to a
   FIFO on an independent clock and the data is transferred in bursts
   during the blanking time. Your pint about the size of the FIFO may be a
   factor as my size is only about 120 frames. But, this method won't work
   very well with the read cycle.
   My other method using a FIFO writing to memory in place of a video read
   isn't the best either because of the "sparkles" I'm thinking my next
   try will be doubling the VGA clock and ( if the RAM is fast enough) do
   an interleave. If I still use the FIFO the CPU/Video clocks can still
   be asynchronous.

   Thanks for the info.. It's very helpful... My project slowly moves
   forward. Two steps forward. 1.98236 steps back.

     On September 13, 2015 at 4:41 PM Mark McDougall
     <msmcdoug at iinet.net.au> wrote:
     On 14/09/2015 5:30 AM, tim franklinlabs.com wrote:
     > So, I'm wondering how others have addressed this?
     How much video memory do you need? For a text-only display far and
     away
     the easiest solution is to use on-chip dual-port RAM.
     Next easiest is interleaved, although it's a little more complicated
     when you want to support multiple clock speeds. But you also get
     deterministic CPU<->memory bandwidth & latencies.
     Then you have caching/pre-emptive schemes which you touch on. I've
     had
     experience with a VGA controller reading from SDRAM that holds off
     the
     CPU and fills a cache (FIFO) at a pre-determined low water mark;
     typically you need several scan lines of data in the cache to
     prevent
     thrashing.
     The Altera VIP core uses FIFO's throughout its architecture for
     access
     to single-port memories quite successfully, and triple frame buffers
     and
     scaling components can be quite bandwidth intensive. Don't be afraid
     to
     use deep FIFO's - deeper than you think you'll need.
     Of course then you'll run into problems if you want to get fancy and
     have CPU code synchronised to blanking periods... but if it was easy
     then everyone would be doing it. ;)
     Regards,
     --
     | Mark McDougall | Error: witty remark not found!
     | <http://pacedev.net> |
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