[Coco] CoCo 1/2 VDG & SAM interaction.

[Darren A]

On Sun, May 31, 2015 at 12:00 PM, Phill Harvey-Smith wrote:

> Hi all,
>
> On the VDG data sheet in the sections under the timing for the memory
> accesses it says that "The VDG may power up using the rising or the falling
> edge of the clock".
>
> Now presumably the SAM needs to detect which edge of the clock the the VDG
> is using so that it can maintain the correct RAM timing and work the data
> hold latch for the VDG.
>
> So does anyone know exactly how the synchronization takes place, I would
> guess that it maybe compares the first transition of DA0 after the end of
> HS with the phase of the video clock (which it of course generates) to
> determine if it changed on a rising or falling edge.
>


The SAM doesn't care which edge of 3.59 Mhz clock the VDG is using. The
datasheet for the SAM explains that there is a 3-cycle window of the 14.318
Mhz clock in which the rising edge of DA0 must occur. If it rises outside
that window, the SAM suspends the VDG clock until a pulse which is
generated in the middle of the window re-starts it.

- Darren