[Coco] A Technical Question

[jdaggett at gate.net]

On 17 May 2012 at 16:02, T. Franklin wrote:

> I have atechnical question about the video link and RAM on a computer (not necessarilya CoCo). I'm creating my own 6809 basedcomputer on an FPGA and stuck on a direction as to implementation. It has to dowith the write CPU cycle of the video area. Is it normal to allow the CPU towrite to video RAM only during the refresh & blanking? If so, is it normalto use a dual port RAM scheme or is the processor held in a wait state until thehorizontal scan is complete? 
> 
> Some of theideas I had with this venture is to (like others) implement a CoCoin an FPGA but modify all the graphics routines (i.e. lines, circles, draws andPCLS) to all FPGA core implementation. I?m thinking about adding a 3D FPGA coreimplementation similar to OpenGL for some real cool CoCogaming.
> This is just mydream but as I slowly get started, I?m finding that questions like this oneplague me for weeks. So any help would be appreciated. 
> 
> See you all atCoCoFest!!!
> 
> 
> 
> 
> --
> Coco mailing list
> Coco at maltedmedia.com
> http://five.pairlist.net/mailman/listinfo/coco
> 
> 
> -----


The Coco line uses what is called IDMA, Interleaved DMA, to access a shared RAM block for 
video and data/program storage. This is done using the twophase clock system of the board. 
The E clock is the controlling clock for periperal access on the MC6809 series of processors. 
When the E clock is low the microprocessor is not accessing any external memory or 
peripherals. Therefore the the video controller can access the memory at that time to read 
data. When the E clock is high then the microprocessor is accessign memory or a peripheral 
device. 

This method is okay up to about clock speeds of about 25MHz. After that, standard dram can 
become to slow. Even static RAM is close to not usable. The reason is that the access time 
for the ram has to be a minimum of twice that of the E clock cycle. So for a 2MHz E clock, 
500nS cycle time, the ram used must be no slower than 250nS access time. To move up to a 
25 MHz E clock speed, 40nS cycle period, the ram used must be no slower than 20nS 
access time. 

There advantages of what the COCO does and disadvantages also. One disadvantage that 
any shared video memory access has to be done based on a multiple of the E clock for the 
6809. Also a disadvantage is the that 10nS SRAM is rather expensive per megabyte. If you 
want 2 megabyte of 10nS SRAM, you better be prepared to plunk down aobut $25 or so. The 
advantage this system is with slower CPU clock speeds.

An example would be with a 2 MHz bus speed for the 6809. The cpu cycle time is 500nS. 
The CPU access of memory/peripheral would be on the second half of the c-pu cycle. During 
the first 250 nS you can read as many bytes as you can depending on how fast the ram 
access is. SRAM at 20nS could read 8 bytes easily during the first 250nS the machine cycle. 
DRAM could be put into burst mode and read as many bytes as the dram will allow in 250nS, 
providing the dram is fast enough to read the desired number of bytes. 

In such a system you would have to pass all the 6809 read data through s controller much 
like the GIME chip to multiplex between the CPU and video controller. It gets a bit nasty, but 
is quite doable especially in an FPGA. 

Then there is the route that most PCs use. Access video during the blanking levels. This 
requires DDR or QDR dram chips to read enough data fast enoough depending on what the 
pixel clock is and the pixels per row and the color depth. Most of the 6809 FPGA designs use 
a single clock and are pretty much limited to about 25MHz bus speed. IDMA would require 
20nS SRAM or faster. DDR ram is 3.5nS, but a more complex controller is needed and with 
the CPU runing at even 20 MHz creates its own problems. 


james