[Coco] New thread, cga-rgb->vga convertor GBS-8220

Mark Marlette mmarlette at frontiernet.net
Thu Jul 28 13:09:00 EDT 2011


Mark,

All good input, thanks! Which raises a question......If the design only needs these base files. Which I know to be true because of the way you create new projects based upon older designs.Why do they then import the database files? Pin files, etc as I know it ARE NOT in the DB files.

I have noticed that .bdf, ,bsf, etc are text files as well. REALLY NICE!

I'll get there. I spoke with one of our VHDL design engineers that I have worked with before on some work products. They all say the same...Once you got it, it is great, just getting there can be challenging. Start slow, simple logic, state machines, etc and learn at your own pace.

Regards,

Mark
Cloud-9


----- Original Message -----
From: "Mark McDougall" <msmcdoug at iinet.net.au>
To: "CoCoList for Color Computer Enthusiasts" <coco at maltedmedia.com>
Sent: Thursday, July 28, 2011 10:51:52 AM
Subject: Re: [Coco] New thread, cga-rgb->vga convertor GBS-8220

On 29/07/2011 1:31 AM, Mark Marlette wrote:

> All
> of our designs are in SVN so when I pull the design up with a new version
> of Quartus, the local repository is modified but I do not commit the
> converted database.

Schematics aside, you need only retain the .qpf, .qsf, source files and any 
extra timing/script files (.sdc, .qip, etc) in revision control. No need at 
all (and a serious waste of space) to retain the 'db' directories, or all 
the other reports and such created in the project directory.

The really nice thing is that - unlike Xilinx tools - With a pure HDL 
(VHDL/Verilog) design, you only ever require *text* files in SVN.

And as you know your .SOF/.POF/.RBF/.JIC bitstream files are all you 
ultimately need to run your design.

> This was done in a
> hierarchical schematic design, currently three levels deep. I am just
> starting to learn .vhdl. Big difference in editing and creating. :)

Went down the same path as you. When you finally switch all your designs to 
HDL your life will be *much* *much* easier! As will revision control! ;)

> I haven't tried it yet but it appears that I can make .v code from my
> schematic design and transfer that file to the new designs.

IIRC you can create VHDL or Verilog from a schematic. It's a little verbose 
and the naming convention obtuse, but it's a great place to start!

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

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