[Coco] 6x09 read and write strobes.

[Phill Harvey-Smith]

Hi all,

I am currently developing a SD/MMC interface for the Dragon and CoCo, 
that uses a Xilinx CPLD to interface between the 6809 and the AVR on the 
board.

I am however having some problems with random lockups / crashes that 
don't seem to be software related as I have tested the software in mess 
and it will run flawless ly there.

The thing I am unsure about is the read and write strobes and which 
clocks they should be based upon.

Currently in my Verilog I have :

// Generate OE and WE signals, only do this if Reset is high !
assign RD			= E & RW & Reset;
assign WR			= Q & ~RW & Reset;
assign nRD			= ~RD;
assign nWR			= ~WR | RamWP;

This way RD and WR are positive logic, so I am latiching into the CPLD 
on the rising edge of WR and outputting to the 6809 bus while RD is 
true. nRD and nWR are the read and write strobes for the onboard ROM and 
RAM, the RamWP is in a latched register and allows me to write protect 
the RAM.

Is this the correct logic ?

I have seen (on the DragonDos schematic, the read and write strobes for 
the WD2797 are similar to the ones above based off both clocks, however 
the write strobe for the drive/density select latch is based off E.

Comments anyone ?

Cheers.

Phill.

-- 
Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !

"You can twist perceptions, but reality won't budge" -- Rush.