[Coco] What would a CoCo successor have to have as a minimum?

[Mark McDougall]

On 21/11/2010 2:41 PM, John Kent wrote:

> I would imagine though that to implement the
> memory controller you'd need a fairly large CPLD, and you'd have to
> multiplex the 32 bit data bus onto a 8 bit CoCo bus. You'd also probably
> need some way of buffering the SDRAM data so that it could be randomly
> accessed by the CoCo. i.e. You'd have to hold the processor if you wrote to
> SDRAM during a refresh cycle.

I would imagine this is a pretty tall order for a CPLD. The pin count alone 
puts you into the high end of the market, and you certainly won't get much 
memory for caching either.

I'm afraid you're looking at a low-end FPGA for this sort of design...

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"