[Coco] POKE 65495,0

[jdaggett at gate.net]

On 31 Jan 2007 at 11:59, Mike Pepe wrote:

> Since reading from ROM doesn't contend with the SAM feeding data to
> the VDG, the E&Q clocks can be sped up while the SAM will still feed
> and latch the VDG data at the normal rate.
> 
> The true double-speed mode takes the VDG time and uses it for CPU.
> That's why the display goes away. It also apparently takes away
> refresh time (since refresh is done during VDG quiet time).
***************
The SAM chip does not work that way. Yes refresh is done when the VDG does 
not need to access memory. That is during the horizontal blanking period. The 
SAM chip can do easily 15 RAS refresh grants irregardless of how fast the E-
Clock is. MPU access to memory will not interfere with refresh. Instread the SAM 
chip multiplexes between refresh and VDG accesses to memory in one half the 
E-Clock and between VDG/Refresh and the MPU during the other half. 

When the E-Clock is 1118nS the SAM chip can do two refresh grants every E-
Clock. When the E-clock is at 559nS it does only one refresh grant per E-Clock 
cycle. 

Also remember that there is a very strict procedure when changing speeds on the 
SAM chip. You cannot go from Fast mode to Slow mode in one step unless you 
do a hard reset. To go from Fast mode to Slow mode you must first place the 
SAM chip in AD mode for at least one machine cycle. You are allowed to go from 
slow mode to fast mode in one jump but I believe it is better to go from slow to 
fast via AD mode. 

james