[Coco] POKE 65495,0

[Darren A.]

>From: Phill Harvey-Smith <afra at aurigae.demon.co.uk>
>
>Darren A. wrote:
> >> From: Diego Barizo <diegoba at adinet.com.uy>
>[snip]
> > *When the SAM control register bits "R1" and "R0" are programmed to
> > "0" and "1" respectively, the Address Dependent Rate Mode is
> > selected. In this mode, the 'crystal divided by 16' MPU rate is
> > automatically used when addressing within $0000 to $7FFF, or $FF00 to
> > $FF1F ranges. Otherwise the 'crystal divided by 8' MPU rate is used.
> > This mode often nearly doubles the MPU throughput while still
> > providing transparent VDG and dynamic RAM refresh functions. For
> > example, since much of the MPU's time may be spent performing
> > internal MPU functions, accesing ROM ($8000 to $FFEF) or accessing
> > I/O ($FF20 to $FF5F), the faster 'crystal divided by 8' MPU rate may
> > be used much of the time.
>
>This I always found confusing, as even when running code from ROM,
>surely whilst display is active the VDG will still be accessing the RAM
>($0000-$7FFF), so as far as I can see one of two things must be happening 
>:-
>
>1) The faster mode is only active during /HS and /VS periods, when the
>VDG is not accessing RAM, though even then the SAM is issuing refresh
>accesses to the RAM.
>
>2) The system is running at double speed all the time, and the VDG
>accesses are only every other cycle (as they are latched anyways).
>
>I suspect the former though. As if the latter where true, assuming
>sufficiently good RAM, then there is no reason why the SAM could not run
>the CPU at double speed all the time and just do a RAM access every
>other cycle, as this is an exact 2:1 ratio.
>
-
Phil, here is another excerpt from the SAM datasheet. Maybe this will help 
clarify things:

The MPU and VDG must both be able to access RAM without contention. This 
difficulty is overcome by taking advantage of the timing and architecture of 
Motorola MPUs (6800, 6801E, 6809E and 68000).

Specifically, all MPU accesses of external memory always occur in the latter 
half of the machine cycle. Similarly, the MC6847 (non-interlaced) VDG 
transfers a data byte in a half machine cycle. Thus, when properly 
positioned, VDG and MPU RAM accesses interleave without contention.

This interleaved Direct Memory Access (IDMA) is synchronized via the MC6883 
by centering the VDG data window half-way between MPU data windows. The 
result is a shared RAM system without MPU/VDG RAM access contention with 
both MPU and VDG running uninterrupted at normal operating speed, each 
transparent to the other.

Darren

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