[Coco] SAM and RAM refresh.

[jdaggett at gate.net]

On 10 Feb 2007 at 17:56, Phill Harvey-Smith wrote:

> Hi,
> 
> I've just as promised had a poke around the sam with a scope when it's
> in double speed mode (poke &hffd9,1), and found the following :
> 
> The CAS and RAS signals seem to always toggle at 1.7MHz, irrespective
> of 
>   the speed selected, in normal mode what happens is that the CPU and
> video access the ram on alternate CAS/RAS cycles, as expected, and in
> double speed the CPU gets an access every cycle and the VDG gets none.
> 
> So as documented on the SAM data sheet, the CPU literally steals all
> of the VDG access, and so no refresh happens.
>

Then what I think maybe the reason behind is this. In 1979 when that chip was designed, I  
believe that 250nS access time DRAM were the state of the art DRAMs. To do interleved 
DMA you have to have 150nS access time maximum at 1.78MHz E-Clock. 150nS access 
time DRAM has a cycle time of 260nS +/-. During one half the E-Clock at  high speed 
mode you have 279nS. 200nS DRAM or slower would not work at high speed for IDMA. 


> The interesting thing I found was that the RAS/CAS still toggle even
> if the CPU is accessing ROM, I guess this is doing a dummy read and
> the gating on the ram data out prevents the read data from reaching
> the CPU data bus.
> 
***********

Yes that makes sense. With two external latches you can use the RAS/CAS lines to latch 
the row and column addresses to drive Static ram instead of Dynamic ram. There is a 
mode that 6847 will go in to do such. DRAMs are not active unless the CE is actively 
asserted. You can clock the RAS/CAS lines all you want and they do nothing. 




james