[Coco] CoCo 3 512k SRAM Upgrade REST OF CIRCUIT
coco at yourdvd.net
coco at yourdvd.net
Sun Apr 22 12:08:16 EDT 2007
UNLESS I HAVE TOTALLY SCREWED UP THIS SHOULD DO IT:
--------------------------------------------------------->TO STATIC RAM
WE*
|
|
*-------------INVERTER-GATE-HERE------------------------->TO STATIC RAM
OE*
|
|
|
|
WE0*------| |
|AND-GATE--------------*-------------------------
WE1*------| | |
| |
| |
| |
------0------ |
| LOW | |
| ENABLED | |
| NON | |
| INVERTING | |
| TRISTATE | |
| BUFFER | |
WE0*---------------------------------------------------------------------------------------->TO
STATIC RAM LB*
| | |
| | |
WE1*---------------------------------------------------------------------------------------->TO
STATIC RAM HB*
| | |
| | |
------------- |
|
-------------------------|
|
------1------
| HIGH |
| ENABLED |
| NON |
| INVERTING |
| TRISTATE |
| BUFFER |
CAS*---*------------------------------------------------------------------------------------>TO
STATIC RAM LB*
| | |
| | |
|--INVERTER-GATE--------------------------------------------------------------------->TO
STATIC RAM HB*
| |
| |
-------------
THE WE0* AND WE1* ARE ANDED TO PRODUCE WE* FOR THE SRAM AND THE INVERSE
OF THIS PRODUCES OE* FOR THE SRAM (NO CHANCE OF BOTH SIGNALS TRYING TO
GO ACTIVE AT THE SAME TIME). DURING A WRITE THE LOW TRIGGERED TR-STATE
BUFFER PASSES WE0* AND WE1* TO THE STATIC RAM TO ACT AS THE LOW BYTE
(LB*) AND HIGH-BYTE (HB*) SIGNALS RESPECTIVELY. DURING A READ THE
ACTIVE HIGH TRI-STATE BUFFER PASSES CAS* AND IT'S INVERSE TO LB* AND
HB* OF THE STATIC RAM. IF I READ THE SCHEMATICS AND TRUTH TABLES
CORRECTLY, THIS SHOULD WORK. ANYTIME A WRITE IS not HAPPENING, THE SRAM
WILL BE IN READ MODE, BUT THIS SHOULD ALL BE HANDLED SEAMLESSLY BY THE
74LS244'S OF THE COCO 3 MEMORY CIRCUIT.
NOW I LEAVE IT UP TO THE REST OF YOU WONDERFUL FOLKS TO TELL ME IF THIS
WILL WORK, AS I HAVE BEEN AT WORK ALL NIGHT, GOT HOME JUMPED RIGHT INTO
THIS AND AM ON THE VERGE OF PASSING OUT FROM EXHAUSTION. - ROB
> -------- Original Message --------
> Subject: Re: [Coco] CoCo 3 512k SRAM Upgrade Z-BUSS DEMULTIPLEX
> From: coco at yourdvd.net
> Date: Sun, April 22, 2007 8:15 am
> To: CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
>
> OKAY, I THINK I MAY HAVE SOLVED THIS. FIRST THIS IS MY SUGGESTION FOR
> DEMULTIPLEXING THE Z-BUS: ---------------- | | RAS*----------|> | |
> OUT| | 8..0|}-----------}TO STATIC RAM | | ADDRESS 17..9 |
> NEGATIVE-EDGE| | TRIGGERED | | LATCH | | | | | | | Z-BUS 8..0----| | |
> | ---------------- ---------------- | | CAS*----------|> | | OUT| |
> 8..0|}-----------}TO STATIC RAM | | ADDRESS 8..0 | NEGATIVE-EDGE| |
> TRIGGERED | | LATCH | | | | | | | Z-BUS 8..0----| | | |
> ---------------- NEXT I WILL INCLUDE WHAT I THINK WILL BE A FUNCTIONAL
> REMAINDER OF THE CIRCUIT. -R > -------- Original Message -------- >
> Subject: Re: [Coco] CoCo 3 512k SRAM Upgrade (Renamed Thread) > From:
> coco at yourdvd.net > Date: Sun, April 22, 2007 7:36 am > To: CoCoList
> for Color Computer Enthusiasts > > I have the service manual in my
> hands. What I'll do is make a truth > table from the access diagrams
> and then we can work from that. The way > memory access is performed
> is different than I originally thought - I > had thought about using a
> 512Kx8 static RAM because I thought the we0 > and 1 signals functioned
> like r/w* lines, but NOT QUITE :-) -r > > -------- Original Message
> -------- > Subject: [Coco] CoCo 3 512k SRAM > Upgrade (Renamed Thread)
> > From: coco at yourdvd.net > Date: Sun, April > 22, 2007 7:24 am > To:
> CoCoList for Color Computer Enthusiasts > > To > Sylvain Rousseau:
> I've renamed this thread. I have been looking > into > your schematic.
> Now, from a quick research of the G.I.M.E. I find > > that a write
> cycle is as follows: The G.I.M.E. writes data by BYTE via > > the we0*
> or we1* 256k bank selects. Whilst a read cycle is as > follows: > The
> G.I.M.E. reads data by WORD, 8 bits via cas low > followed by >
> latching the next 8-bits on cas rise and reading it from > the latch.
> (I > am using ''WORD'' to represent 16-bits, but it's had > so many
> meanings > over the years...) This will help later on in the > day as
> I work on > this. Anyway, your schematic indicates that you are >
> using > negative-edge triggered latches to demultiplex the z-bus. If >
> this is > the case, the inversion of the ras and cas prior to entering
> > the > latches should be removed. However, I need to find the CoCo 3
> > timing > diagrams, if I had those, I could solve this in a few
> hours. > Are they > online? Perhaps a copy of the CoCo 3 Tech Ref
> Manual and/or > service > manual - if anyone knows of a readily
> available download of > these, I > could solve this in a couple of
> hours. I work best from > truth tables > and timing diagrams rather
> than schematics. > Theoretically, during a > read cycle, both we0 and
> we1 should be high, > but if there is the > slightest chance that this
> isn't the case, > ANDing the two signals > cannot be used to generate
> the *we signal. > But I need to go search for > the timing diagrams.
> Any info anyone > might have would be appreciated, > because CoCo 3
> RAM access is > actually amazing that it even works > considering one
> byte of the word > is latched then fed to the gime and > finally to
> the cpu - propagation > delay from hades, I would think... > I'll keep
> digging - rob > > -------- Original Message -------- > > Subject: Re:
> [Coco] Re : Re : > FREE Services For Members Of The > CoCoList > at
> Malted Media > From: > coco at yourdvd.net > Date: Sun, April > 22, 2007
> 5:33 am > To: CoCoList > for Color Computer Enthusiasts > > I > see
> what I believe may be some > potential problems with the schematic > >
> but before I go and make a > fool of myself, I am going to go fetch
> the > > data sheet for the sram > and examine the gime memory timings.
> I'll > get > back to you in a few > hours. -rob > -------- Original
> Message > -------- > > Subject: [Coco] > Re : Re : FREE Services For
> Members Of > The CoCoList > at > Malted > Media > From: Sylvain
> Rousseau > Date: Sat, > April 21, > 2007 4:22 pm > > To: CoCoList for
> Color Computer Enthusiasts > > > Yes, > Mr. > Merchberger host it for
> we at this address: > > > >
> http://zmerch.30below.com/coco/coco3sram.pdf Thank you again Mr. > > >
> > Merchberger. Sylvain ----- Message initial ---- De : Mark Marlette ?
> > > > > : coco at maltedmedia.com Envoy? le : vendredi 20 avril 2007, 13
> h 16 > > min > > 11 s Objet : Re: [Coco] Re : FREE Services For
> Members Of > The > > CoCoList > at Malted Media IIRC there were some
> level problems > in > your > circuit. I > think you posted a .jpg of
> it. I looked at it > > quickly. > Don't totally > remember. Working
> other designs and > > sometimes they all > run together. > Heck maybe
> it was my levels that > > were off.... :) Mark > Quoting >
> coco at yourdvd.net: > What 512k > static > ram are you using? the >
> first to > hit the scene were > > semistatic > requiring something
> like an > 8ms? > refresh or so (these > were > > hitachi). The current
> ones are > fully > static. The 4464 > used in the > 128k > machine use
> a > bidirectional i/o > line like the > static rams. > The 41256 > has
> a > seperate din and dout > line but > these are shorted > together in
> the > > coco 3 memory circuit. > did > you account for the > 256k bank
> switch? > > > if all else fails you > > can make one of these: > > > >
> > >
> ftp://ftp.maltedmedia.com/coco/TUTORIALS/How_To_Upgrade_To_512k_Without_A_Commercial_Memory_Board.zip
> > > > > > D?couvrez ce qui fait jaser les gens ! Visitez les groupes
> de > > > > l'heure sur Yahoo! Qu?bec Groupes.
> http://cf.groups.yahoo.com/ > -- > Coco > > mailing list
> Coco at maltedmedia.com > > > >
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