[Coco] CoCo 3 display offset question.

[Phill Harvey-Smith]

Hi,

Can anyone tell me if on the CoCo 3 the display generation in the GIME 
goes through the mapped memory or if it is limited to a particular block 
(or blocks). A quick check using mess seems to suggest that it honours 
the tradition display offset regs at $FFC6-$FFD3, but I just verified 
this with a quick 4 line basic program, which will have had the mapping 
regs turned off (well CoCo 1/2 compatible mode anyway).

I'm asking as one of the things I am working on is to use a 1M 30 pin 
SIMM, and build a banked system for the CoCo 1/2 & Dragon, using a CPLD, 
  a small SRAM to do the banking. The current design however takes the 
Address bus input to the SAM, and modifies this through the bank 
registers before it goes into the SAM. This should work as far as the 
CPU is concerned, but a side effect may well be that the CPU and the VDG 
will see the display memory differently, whilst this probably won't be a 
problem it's something I'll have to bear in mind :)

Cheers,

Phill.

-- 
Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !

"You can twist perceptions, but reality won't budge" -- Rush.