[Coco] FPGA CoCo

[Gene Heskett]

On Sunday 26 March 2006 23:10, jdaggett at gate.net wrote:
>Gene
>
>Yes that is 6.25 MHz.
>
>Looking at other open 8 bit cores that are out there, most seem to be
> able to run at clocks speeds of 25 to 35 MHz for the FPGA. These are
> usually Z80, 8080, and 6502 variants.
>
>I diverted some of my time from the GIME chip to look at doing a
> 6809/6309 CPU core. The idea is to write the code using microcoded
> instruction set unlike the 6809 random logic. So far I have
> instruction decode and post byte decode logic that is rather quick. 
> In an FPGA the instruction and postbyte decodelogic can be done in
> around 6.8 nS propogation delay. That is from the time that the
> instruction register is loaded the address mode and instruction type
> will be known within less than 7 nS. Using four clock cycles per
> machine cycle, that would correlate to a current 6809 running at
> about 30 MHz. The biggest delays now seem to be the routing of
> internal busses and signals within the FPGA. They are as much as the
> logic propogation delays.
>
>Last need for time analysis that I want to do is for the a 16bit
> ALU.What I want to know is how long it takes for the output from the
> time the ALU gets two inputs.The ALU function is for addition,
> subtraction and logic. If that can equal 7 nS delays then a 30 to 35
> MHz 6809/6309 could be possible in a FPGA. Love to see if I can
> design a multiplier and divider that will not take up a whole lot of
> area and still be faster than the current multiplier used in the
> 6809, 11 machine cycles.
>
>The whole goal is to get a 6309 based COCO3 in a single low cost FPGA
> that will interface to a VGA/SVGA monitor. Also to run at least
> equivalent to a current 6809 at 25Mhz. A supercharged Coco 3. It is
> the only way to get a Coco 3 to achieve higher color depth and video
> resolution is to increase the video bandwidth by increasing CPU
> speed.

Yes, one of the problems with the scan doublers is the s/h rate, the 
gime output slew rates aren't fast enough to make clean doubled video 
for all channels, or at least thats what I'm observing here.  It looks 
quite good in most cases, but the gimes output driver slew rates 
definitely are a problem.  A full scale black to peak white swing is 
well over 220ns according to my measurements here.  A 1 pixel wide line 
only makes it to about 30% amplitude.

This is beginning to sound rather appetizing James.  Do keep us posted, 
and see if you can come up with a cost for the finished version.  Then 
another question sticks up its hand and waves for attention, & that is: 
Are you going to do an interface that will let us use our current 
cartridges, disk, seriel etc cards as we now use them in the multipack.  
Or is that so far down the road its not a visible object yet?

It seems that the cartridge port would be the ideal place to draw a line 
between all new stuff, and making use of our existing hardware.

>
>james
>
>On 26 Mar 2006 at 20:56, Gene Heskett wrote:
>> On Sunday 26 March 2006 19:14, jdaggett at gate.net wrote:
>> >Gene
>> >
>> >Based on what John has done, his 6809 is running at 12.5 MHz with a
>> > single phased clock. I am not sure if his core runs single clock
>> > for each intructionor not. Even at two clock cycle per instruction
>> > would yield an effective 6025 MHz. By synthesizing the the CPU
>> > core alone, static timing indicates that a single instruction may
>> > operate up to about 19 MHz.
>> >
>> >james
>>
>> Kewl!  I assume you meant 6.25 mhz above, which is still a coco on
>> nitros.
>>
>> --
>> Cheers, Gene
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-- 
Cheers, Gene
People having trouble with vz bouncing email to me should add the word
'online' between the 'verizon', and the dot which bypasses vz's
stupid bounce rules.  I do use spamassassin too. :-)
Yahoo.com and AOL/TW attorneys please note, additions to the above
message by Gene Heskett are:
Copyright 2006 by Maurice Eugene Heskett, all rights reserved.