[Coco] [Color Computer] Re: OS-9 as Replacement for DECB.

jdaggett at gate.net jdaggett at gate.net
Sat Sep 3 15:42:41 EDT 2005

On 3 Sep 2005 at 3:44, James Diffendaffer wrote:

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From:           	"James Diffendaffer" <jdiffendaffer at yahoo.com>
Date sent:      	Sat, 03 Sep 2005 03:44:50 -0000
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Replacement for DECB.
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> If you want a 6809 to run at 250MHz think pipelined... it's been done
> for the Z80 and it simulates at above 250MHz or something like that in
> something you could actually use.  Split a CoCo into a CPU and the
> rest of the hardware with two chips and you could include a lot of
> other stuff (I have some suggestions and VHDL to go with it if you are
> interested).

I have seen a Verilog Z80 core that will do up to  250 MHz in a 0.13 micron ASIC. In 
FPG A that is considerably slower. Even at 35 MHz is still fast. 

I have thought of that two chips, CPU and the rest.  Designwise is nicer but what I 
want to accomplish would man a larger PCB and I am try  ing to get as small as 
possible. One thin that I have thought of is increasing the Program Counter to 24 

It maybe worth a looksee at what you  have!

> After looking at the 6309 I don't know if a complete duplicate is the
> way to go or not.  I think it would be better to add a large register
> mode similar to what has done with some of the new Z80 decendants.  A
> 24 bit address buss and registers would solve a lot of problems and
> eliminate paging.  Part of the reason I started messing with GCC was
> because I needed a C compiler.  The other reason was to see if
> supporting such a CPU would be feasable.  A large flat memory model is
> a lot easier to support from C than lots of 8K pages of RAM.
There is some usage for some of the new instrtuctions. Increase in registers is nice 
but to what extent and how many? I can agree with a 24 bit address buss. 

> I also think caching the DP page and page 0 would offer a big speed
> improvement... but I haven't found enough in the way of VHDL cache
> implementations (on no free ones anyway) to check it out.  That also
> makes GCC's use of memory registers very efficient and actually an
> advantage since things can be stored in a fast memory register that
> otherwise couldn't take advantage of Page 0.  A couple 16 byte
> instruction caches would also help a lot.  Thats enough to keep many
> loops in cache and reduce memory accesses.
Not sure if cahing the DP register will gain any speed,especially if you add at least 
the 6309 register sets. 
> The 6309's extra registers yes, illegal instruction traps yes... but a
> lot of the 6309 instructions wouldn't offer any advantage once you
> switch to a pipelined architecture and add cach.  

Pipelineing may not be approach. 


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