[Coco] [Color Computer] Re: OS-9 as Replacement for DECB.

James Diffendaffer jdiffendaffer at yahoo.com
Fri Sep 2 23:44:50 EDT 2005


> Right now there is a 6809 core that fits into a Spartan 2e 200K gate
> part that will run at 12.5 MHz. I have a copy and one day would like
> to expand it to incorparate the 6309 instruction set. Also I think I 
> can do a few th ings to speed it up to amy be 25 MHz or more. 
> Dangit,if there is a free 8080 core out there that can run at 30 MHz 
> then by gosh I can't see why a 6809 core can't!

> My dream would be to win a lottery and be able to go to ASIC with a 
> 6309 compatible processor with improvements. At .13 micron  
> technology, it would not be to difficult to get the part to run at 
> around 250MHz. But I need upward to a half a million dollars to pull
> it off.

If you want a 6809 to run at 250MHz think pipelined... it's been done
for the Z80 and it simulates at above 250MHz or something like that in
something you could actually use.  Split a CoCo into a CPU and the
rest of the hardware with two chips and you could include a lot of
other stuff (I have some suggestions and VHDL to go with it if you are

After looking at the 6309 I don't know if a complete duplicate is the
way to go or not.  I think it would be better to add a large register
mode similar to what has done with some of the new Z80 decendants.  A
24 bit address buss and registers would solve a lot of problems and
eliminate paging.  Part of the reason I started messing with GCC was
because I needed a C compiler.  The other reason was to see if
supporting such a CPU would be feasable.  A large flat memory model is
a lot easier to support from C than lots of 8K pages of RAM.

I also think caching the DP page and page 0 would offer a big speed
improvement... but I haven't found enough in the way of VHDL cache
implementations (on no free ones anyway) to check it out.  That also
makes GCC's use of memory registers very efficient and actually an
advantage since things can be stored in a fast memory register that
otherwise couldn't take advantage of Page 0.  
A couple 16 byte instruction caches would also help a lot.  Thats
enough to keep many loops in cache and reduce memory accesses.

The 6309's extra registers yes, illegal instruction traps yes... but a
lot of the 6309 instructions wouldn't offer any advantage once you
switch to a pipelined architecture and add cach.  

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