[Coco] [Color Computer] Is this likley to work ?

[Phill Harvey-Smith]

Hi,

I am toying with the idea of developing some sort of expansion RAM for 
the CoCo 1/2 & Dragons, basically the non-gime machines. I'm just trying 
to bounce the idea here to see if it is likley to work.

Looking at the circuit sheets for the Dragon & CoCo 1, it seems that 
access to the RAM is mediated by the SAM, and the LS244 buffer on the 
output of the RAM. Also reading the datasheet for the 4164 RAM chip, it 
seems that /RAS is used as a chip enable to set it up to be accessed.

The other complication of course is that the RAM is accessed both by the 
  CPU and by the VDG, however all CPU accesses IIRC, happen with E high, 
and VDG with E low.

Based on this is should be possible to gate the RAS signal to the RAM, 
and the enable signal to the LS244, to effectivly isolate the processor 
and RAM databus. You would obviously want to only do this when E is 
high, so that the VDG can still get RAM access and the RAM would still 
get refreshed.

With the CPU and RAM databus isolated, it should be possible to build 
some decode logic to give the CPU an address space of greater than 64K,
you would still need to be able to page in the SAM controled RAM so that 
you could put data in it for the VDG to display, but withe the right 
logic you could page in just say an 8K page (as on the CoCo3).

Is my logic sound, or am I just going slightly mad :)

Both of course can be true.....

Cheers.

Phill.


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