[coco] 6309 speed

[Gene Heskett]

On Wednesday 03 August 2005 11:09, jdaggett at gate.net wrote:
>Gene
>
>I seriously doubt that 20 to 30 MHz speeds could be obtained. At
> least not operating at 5VDC.  Maybe at 6.5 VDC. More realistic is 5
> to 10 MHz. The problem wil lbe not all will do that. Maybe 1% of
> all 6309 will do 10MHz. Maybe 50% will do 5 MHz.
>
>Output waveforms alone are not a sufficient means of estimating the
> speed of a processor. The determining factor is the internal logic
> used to do the Instruction decode, addressing mode decode and ALU
> function. The problem is the delay time through the logic and the
> routing of busses through the chip. The 6809 uses a combination of
> synchronous and asynchronous logic. It is the asynchronous logic
> that is of most concern.

Which is why I mentioned the glitches on some pins early in the cycle.  
If those are going to represent a fixed delay from the clock pulse, 
then I can see problems well before 30 mhz, possibly as low as 8 or 
10 mhz.  IIRC, they were about 30-45 ns after the clock edge, but I 
don't recall which clock or which edge now.  At the current speed, 
they are rather benign, and any ttl buffering done will probably 
gobble them up.  They aren't full swings by the time they get thru 
the buffering in the late mpi I have.

>Some designs try to do instruction decode and address mode docode in
> the same logic. While this may save area on the die,it can also
> slow things down as it may increase levels of gates in which two
> independent outputs must be obtained. A typical adress mode decode
> logic can be up to five levels of logic gates. In fabrication
> processes today one level of gate delay can be as little as 1 nS.
> Five levels now increases that to 5 nS delay and then you add
> anywhere from 1 to 2 nS for routing. Processes used to make ICs 25
> yrs ago were slower.
>
>In designing the logic for a CPU, there is a trade off of speed and
> area. Sometimes to gain speed, processes need to be split up and
> thus take up more area. With the processes today pushing
> transistors that can switch at near one TeraHertz and junction
> widths that can be measured by the number of atoms across, are
> becoming realiazable. This allows for efficient use of area and
> parallel task to improve speed.
>
>james
>
>On 3 Aug 2005 at 6:40, Gene Heskett wrote:
>
>Date sent:      	Wed, 03 Aug 2005 06:40:43 -0400
>From:           	Gene Heskett <gene.heskett at verizon.net>
>Subject:        	Re: [coco] 6309 speed
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>> Having looked at the waveforms coming out of it and finding that
>> edge transitions are in the 10 nanosecond territory, my guess is
>> that it could probably go quite a it faster, possibly as high as
>> 20-30 mhz. The only thing that would worry me is that there are
>> some glitches on the address lines that would, if they occur a
>> fixed time after a clock transition, begin to impinge on the
>> memories 'setup' time when the clock speeds rise.

-- 
Cheers, Gene
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