[Coco] FPGA VS Software Emulators

[Walter Zambotti]

Dave wrote:

>So the input clock bears little hint as to the rate things are happening inside your device. eg the 
>above-mentioned examples with a 50MHz clock are actually running quite slowly (~25MHz) inside. 
>Contrast that with a design I've worked on with a 24MHz input clock; running logic at 150MHz and >DRAM at 4-500MHz...

Leslie wrote:

>At it's current top speed of 25MHz, that represents a 40ns cycle time.
>Each cycle has a potential CPU and VIDEO access to the SRAMS, so the SRAMS are being accessed at no faster than 20ns at present.

So to me it sounds as if the emulated CPU and GIME are functioning like real separate physical devices that require interleaving to the memory.

That’s amazing!

So even though there is just one FPGA unit the emulated CPU and the emulated GIME(GPU)  both behave as two separate devices!

So they must run in parallel!

I'll say it again, that's amazing!

How much parallelism can occur in these FPGA devices?

I suppose the down side is the maximum speed of the memory accesses will only be half as fast of what they could be!

Walter

-----Original Message-----
From: Coco [mailto:coco-bounces at maltedmedia.com] On Behalf Of Dave Philipsen
Sent: Wednesday, 26 July 2017 12:45 PM
To: coco at maltedmedia.com
Subject: Re: [Coco] FPGA VS Software Emulators

As Mark said, the 6809 core in the CoCo3FPGA runs at 25 MHz and the VGA dot clock is also conveniently 25 MHz.  Remember that the real CoCo 3 interleaves CPU access to the memory with video system access so I think it works out well when the CPU clock matches the dot clock in this case.

And if anyone's interest has been piqued feel free to email me and I can send you an invitation to the CoCo3FPGA group.  You don't need to own an FPGA system to be a member; just a desire to snoop around and see what's going on over there.

You can also go to: https://groups.yahoo.com/neo/groups/CoCo3FPGA/info
and make a request for membership.


Dave


On 7/25/2017 7:45 PM, Mark McDougall wrote:
> On 26/07/2017 10:30 AM, Mark McDougall wrote:
>
>>> Cyclone® IV EP4CE22F17C6N FPGA
>>> runs at 50 MHz.
>>> Altera Cyclone II 2C20 FPGA
>>> runs at 50 MHz.
>
> For those interested, the input clock to an FPGA is usually chosen 
> with regards to the desired clock frequencies inside the design. By 
> using multipliers and dividers FPGA PPLs have limits on the resolution 
> of generated frequencies, so if you have a particularly critical 
> frequency you need then you'd better make sure your input clock is a 
> "nice" frequency. There are even further constraints when generating 
> multiple frequencies from the one PLL (input clock), which is often 
> the case, and more-so again in smaller devices.
>
> Often parts of your design that don't have a specific frequency 
> requirement will run at a "convenient" frequency based on what the PLL 
> can output.
>
> So the input clock bears little hint as to the rate things are 
> happening inside your device. eg the above-mentioned examples with a 
> 50MHz clock are actually running quite slowly (~25MHz) inside. 
> Contrast that with a design I've worked on with a 24MHz input clock; 
> running logic at 150MHz and DRAM at 4-500MHz...
>
> Regards,
>


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