[Coco] FPGA VS Software Emulators

[Mark McDougall]

On 26/07/2017 10:30 AM, Mark McDougall wrote:

>> Cyclone® IV EP4CE22F17C6N FPGA
>> runs at 50 MHz.
>> Altera Cyclone II 2C20 FPGA
>> runs at 50 MHz.

For those interested, the input clock to an FPGA is usually chosen with 
regards to the desired clock frequencies inside the design. By using 
multipliers and dividers FPGA PPLs have limits on the resolution of 
generated frequencies, so if you have a particularly critical frequency 
you need then you'd better make sure your input clock is a "nice" 
frequency. There are even further constraints when generating multiple 
frequencies from the one PLL (input clock), which is often the case, and 
more-so again in smaller devices.

Often parts of your design that don't have a specific frequency 
requirement will run at a "convenient" frequency based on what the PLL 
can output.

So the input clock bears little hint as to the rate things are happening 
inside your device. eg the above-mentioned examples with a 50MHz clock 
are actually running quite slowly (~25MHz) inside. Contrast that with a 
design I've worked on with a 24MHz input clock; running logic at 150MHz 
and DRAM at 4-500MHz...

Regards,

-- 
Mark McDougall
<http://retroports.blogspot.com.au>