[Coco] 6309/6809 opcodes with mixed 8/16 bit registers

[jdaggett at gate.net]

On 18 Nov 2012 at 15:32, Harry Hurst wrote:

> Lately, I've been cleaning up some of the clutter that I've accumulated,
> and I've run across a lot of stuff that I had forgotten about. One of them
> was a simulator for the 6x09 that I started back in '90. I think I'd like
> to finish it so I started looking it over a bit. I've found some errors,
> but the biggest problem I have presently is info on what happens when the
> two CPU's when they encounter the unexpected. On the 6309 I know there is
> a trap for invalid opcodes that takes it to the vector stored in $FFF0.
> (It also sets MD.6 so it can be distinguished from a divide by 0 trap,
> which shares that vector) So here are my most pressing questions:
> 
> 1> Does the 6809 just execute an effective NOP on an illegal opcode? Or
> does it decode the illegal opcode as a nearby opcode?
>

Some 6809 undefined opcodes will decode as defined opcodes. Others will not decode. 
Should this happen, then the 6809 will reset if my memory serves me correct. 

The 6309 calls a trap vector so that the OS and/or program will handle that vector. 

> 2> Does anyone have any info on what would happen if a 6x09 would execute
> opcodes like TFR or EXG with mixed 8 and 16 bit registers specified? Do
> both the 6809 and the 6309 behave the same in this case?
>

IF it got pass the assembler, the 6809 will only transfer like registers. That is the source and 
destination register must be of the same width.

that is about all I can help on. 

james