[Coco] CoCoFest Online - For those that just simply could not go.

[John Kent]

Should have gone to the list.
I have not really done an exhaustive check of patents.

John.

On 26/05/2011 10:28 PM, John Kent wrote:
> Hi James & Boisy,
>
> Yes, my design uses  what really boils down to microcoded state 
> machine, although the next address or state is coded into the state 
> machine rather than using a microcode Program Counter. On the 6809 I 
> do have a state stack, so that I can share the addressing modes across 
> all of the instructions. The addressing modes are microcode subroutines.
>
> The 68HC11 is similar to the 6809 although is probably closer to the 
> 6800 or 6801 and can execute pretty well all the 6800 instructions. 
> opcode extensions allow for the additional Y index register. I do have 
> a 68HC11 design called System11 but I never bothered to complete it. 
> The progression was: Micro8, System05 (68HC05) which I never quite 
> finished, System68 (6800), System01 (6801/03), System11 (68HC11) which 
> I never quite finished, and System09 (6809).
>
> They were all pretty similar in design, except for the 6809 I 
> implemented a microcode or state stack.
>
> I used the ALU to do all the index register calculations which meant 
> that the ALU had to be 16 bit. You could have a 16 bit address 
> generator for the index registers, stack pointers and program counter 
> and an 8 Bit ALU for the accumulators.
>
> It's not just the state sequencer that slows the design down, it's 
> also the size of the multiplexer to the left and right side of the ALU.
>
> My 6809 design uses a single phase clock. The clock is used to clock 
> the new registers into including the program counter and the 
> transition state of the sequencer. I use the falling edge as with the 
> 68XX although FPGA designs normally use the rising edge. The address 
> and data are normally set up before the rising edge, mid cycle, rather 
> than by the quadrature clock, so that the rising clock edge can be 
> used for reading and writing block RAM.
>
> Ideally I'd like to use the wishbone bus although the SRAM and SDRAM 
> typically need a faster clock than the CPU, i.e. 50MHz rather than 25MHz.
>
> I'd like to do a 6309, but I'm concerned if I spend the time on it 
> that I would get some remuneration for it.
>
> John.
>
> On 26/05/2011 1:41 AM, jdagget at gate.net wrote:
>> John
>> I tend to concur that adding the instructions for the 6309 may very 
>> well start to slow down the
>> buss speed. The real concern is the increase in logic in your state 
>> control process. Operating
>> the 6809/63090 at buss speeds at other than submultiples of the pixel 
>> clock will cause some
>> minor issues with the GIME chip or other video control logic timings. 
>> It is neater to just use
>> sub multiples of the pixel clock like the GIME/VDG chips do. Just 
>> neater.
>>
>> I have actually looked at doing a variant based on the patents for 
>> the 6800 and the four
>> patents that I found that directly apply to the 6809. Also one can 
>> look at what the University of
>> Florida students did with the GATORHC11.  That is a micro coded 
>> machine that maybe
>> modifiyable to the 6809/6309 usage. You would be surprised to know 
>> that the internal
>> structure of the HC11 and the 6809 are more similar than one would 
>> think. The HC11 is not
>> microcoded. Its instruction set is not totally unlike that of the 
>> 6809 either.
>>
>> Also the address bus in the 6809 is two 8 bit busses and the data 
>> buss is also two 8 bit
>> busses. The 6809 design uses bus switches in key locations to route 
>> data in and ou and
>> between registers. Also the PCR has its own incrementer and does not 
>> need to pass the
>> PCR increment through the ALU. The output of the incrementer is 
>> routed back through the
>> address bus to the input of the PCR through bus switches. Granted 
>> this is all dreived from
>> drawings and some of the patents on the 6800/6809 series of 
>> processors. I know that the
>> switch concept is nearly impossible to duplicate in an FPGA. Though 
>> the routing can be done
>> with muxes.
>>
>> Also to consider this the 6809/6309 does use a quadrature clock. This 
>> gives four states per
>> clock cycle to do the internal routing with in the processor. I know 
>> many FOGA circuit
>> designers do not like using both positive and negative edges in their 
>> designs. And quadrature
>> clocks may not be as popular either. The quadrature clock system give 
>> the 6809 its speed
>> advantage over it competitors of that time. Slower clock meant less 
>> current.
>>
>>
>>
>> james
>>
>

-- 
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent