[Coco] DMA in (Nitr)OS-9 LII?

[Robert Gault]

L. Curtis Boyle wrote:
> On Sun, 23 Jul 2006 18:42:47 -0600, Joel Ewy <jcewy at swbell.net> wrote:
> 
>> I'm not sure about the Sardis, but the Disto SCII has an on-board 
>> SRAM   and an 8-bit counter.  The counter provides the address for 
>> the  SRAM  and is clocked by the disk controller whenever data is  
>> ready.  An  entire 256-byte sector is buffered in the SRAM, and  then 
>> an IRQ is sent  to the 6809E.  Then an interrupt service  routine 
>> copies the contents of  the SRAM into the driver's buffer area.
>>  In essence, it is a simple DMA design, but instead of Directly   
>> Accessing the compouter's main Memory, it is accessing an auxiliary   
>> cache, which the CPU can then access on its own time frame.  And  
>> this  would be one way to use a DMAC like the 6844 in a CoCo -- put 
>> it   between the CPU and some peripherals, and have it fill up a 
>> static RAM   that the CPU could plunder at its leisure.  You wouldn't 
>> get quite  the  efficiency of traditional DMA, but you would reduce 
>> interrupts and   eliminate the need for the processor to wait for slow 
>> I/O devices,   giving more time back to the 6809 to run user 
>> processes, and keep the   clock from losing time.
>>  One implication of Disto's design is that you can't use the SCII to   
>> access PC disks in no-halt mode, because the sector buffer is only 
>> 256   bytes.  I always had to load up a halt-mode floppy driver when 
>> I  wanted  to run the PCDOS util.
>>  JCE
>>
> 
>     Sardis worked the same way, but with an 8K buffer.
> 

With a small amount of hardware modification, the Disto SCII can extend 
the addressing for the SRAM so that 512 byte sectors can be handled in 
no-halt mode. I have this mod on my SCII and can read PC disks in 
no-halt mode.