[Coco] [color computer] Just imagining...

[Diego Barizo]

That sounds a bit like Sockmaster's CoCo 4...
http://www.axess.com/twilight/sock/cocofile/coco4.html

Diego


Mike Pepe wrote:

> I had a couple of ideas. One that comes to mind is to simply let an 
> additional CPU to utilize the bus when the primary is idle or busy 
> executing an internal instruction. That sounds like what Phill 
> mentioned before- a circuit that uses TSC/LIC/BS/BA lines to arbitrate 
> the bus (6809E was designed with this in mind)
>
> The IDMA concept is, of course, what the 6847/6883 combo in the CoCo 
> does. E high=CPU, E low=VGA. You can substitute another 6809 to 
> operate during E low, or a 6844 DMA controller, etc. Unfortunately 
> this won't work in a CoCo since that dead time is taken up by the VDG.
>
> My plan was to break one cycle into 4 pieces. essentially a 4 phase 
> system where each component lags 90 degrees. 3 CPUs can get 3/4 of the 
> cycle and the last can be for video/refresh if DRAM is used.
>
> Unfortunately this needs a lot of latches and 60ns memory!
>
> Probably something that could be hacked into a FPGA/CPLD array.
>
> Anyway, that's what I was thinking.
>
> -Mike
>