[Coco] MC4517 DRAM questions

[Mathew Boytim]

    On Wednesday, March 15, 2023 at 06:23:04 AM EDT, Richard Cavell via Coco <coco at maltedmedia.com> wrote:  
 
 I’ve found a datasheet here for the MC4517 DRAM chip: https://orchidsound.com/mcm4517p12-dram-16-384-bit-16k-x-1-120ns-pdip-16-motorola/

I wonder if I’m reading the datasheet correctly.

1. Is it correct for me to consider that the 7 bit row and 7 bit column addresses could be concatenated into a 14 bit address?

Yeah typically you multiplex the address bus to the DRAM in this case A13-A7 for the row address and A6-A0 for the column address.  Doesn't matter which addresses for row and column but for page mode you would typically use the low bits for the column.
2. Since the chip provides only 1 bit of memory per access, would it be typical to arrange 8 of them in parallel?

Yeah typically you would use 8 in parallel for bytewide memory.
3. The datasheet says that it dissipates 14 mW (Standby). What exactly does standby refer to?

See the ICC4 test case - I guess the chip enters standby when RAS and CAS are deasserted.
4. It has 3-state data output. Does this mean that the default output is high-impedance? When does it produce this output?

Yeah see the timing diagrams for the Q output but I think it is usually driven when CAS is asserted low.
5. It has early-write common I/O output capability. What does this mean?

I'm not sure what that means.
6. The refresh is said to be 64K compatible. I don’t understand what this means.

I'm not sure what that means.
7. Does it have to be refreshed every 2 milliseconds?

Yeah all 128 rows need to be refreshed every 2mSec.  That is pretty typical for 128 rows.
8. It has a hidden /RAS only refresh capability. What does “hidden” mean?

Again refer to the timing diagrams.  But basically while you are reading data with CAS asserted low you can perform refreshes using RAS.
Matt
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