[Coco] Pipelined 6809 microprocessor IP

Kevin Phillipson kevin.phillipson at gmail.com
Sun Dec 20 16:51:26 EST 2020

Hi everyone. I thought you guys would be interested in our graduate
research project - the Turbo9. My friend Michael and I are developing a
modern version of the 6809 that can be used as a small microprocessor IP in
ASICs and FPGAs.

I believe our design is the first pipelined architecture to implement the
6809 instruction set. We are about 5 times faster clock for clock than a
regular 6809 and running at over 100MHz in modern FPGAs. In a cutting edge
ASIC built in a 5nm process we would probably be in the neighborhood of

We make no attempt to emulate the same bus as the original 6809 b/c we are
using the Wishbone bus standard. So I doubt you would see this IP in any
CoCo FPGA designs. Our goal is to create a professional level IP for use in
modern SoCs and 6809 ISA really fit our needs well.

Regardless, I think you might find our work interesting and I want to thank
the CoCo community for preserving all the 6809 resources we used as a

Final presentation video for this semester:
(Note: youtube allows you to watch at 1.5x speed!)

Presentation slides:

The verilog code, microcode & microassembler source uploaded to github:

We are currently looking to pursue our Master's Thesis to complete the
project over the next couple semesters.

Let us know you think!
Kevin & Michael

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