[Coco] WiFi modem.

[Dave Philipsen]

Well, I guess I would try to design it and debug it to the best of my 
ability so that it likely wouldn't need updates in the field. However, 
you can get a generic Altera "byte blaster" for under 5 bucks off eBay 
and I've been told that there is a way to have just the programmer 
portion of the Quartus software without the full-blown installation. I 
don't have any experience with a simpler form of field updating although 
it should be possible.  Essentially you're just blasting information 
into a serial flash chip my means of a JTAG interface and I suppose if 
you had direct access to the flash chip the JTAG interface wouldn't be 
necessary.

Dave


On 1/20/2018 4:12 PM, RETRO Innovations wrote:
> On 1/20/2018 3:58 PM, Dave Philipsen wrote:
>> I think an FPGA implementation of a 6551 would be a fairly easy thing 
>> and would not require a huge FPGA. I have a few projects where the 
>> synthesis of a nice 6850-compatible UART with a 16 byte receive 
>> buffer requires less than 350 LEs including the baud rate generator.  
>> I have used it with data rates up to 1Mbps and it works great. You 
>> could even design a UART that could switch between being a 6850 and a 
>> 6551 with the flip of a switch. Other options could perhaps be added 
>> that would allow larger receive/transmit buffers, non-standard bit 
>> rates, etc, etc.
> If you're game, I'd love to collaborate on something like this. The 
> Verilog and such is straightforward, but I'm stuck with how to 
> implement field updates.  I have some small uCs to use, but I've never 
> connected an FPGA to a uC for re-programming.
>
> Jim
>
>