[Coco] FPGA VS Software Emulators

Joel Rees joel.rees at gmail.com
Wed Jul 26 01:14:11 EDT 2017


On Wed, Jul 26, 2017 at 9:45 AM, Mark McDougall <msmcdoug at iinet.net.au> wrote:
> On 26/07/2017 10:30 AM, Mark McDougall wrote:
>
>>> Cyclone® IV EP4CE22F17C6N FPGA
>>> runs at 50 MHz.
>>> Altera Cyclone II 2C20 FPGA
>>> runs at 50 MHz.
>
>
> For those interested, the input clock to an FPGA is usually chosen with
> regards to the desired clock frequencies inside the design. By using
> multipliers and dividers FPGA PPLs have limits on the resolution of
> generated frequencies, so if you have a particularly critical frequency you
> need then you'd better make sure your input clock is a "nice" frequency.
> There are even further constraints when generating multiple frequencies from
> the one PLL (input clock), which is often the case, and more-so again in
> smaller devices.
>
> Often parts of your design that don't have a specific frequency requirement
> will run at a "convenient" frequency based on what the PLL can output.
>
> So the input clock bears little hint as to the rate things are happening
> inside your device. eg the above-mentioned examples with a 50MHz clock are
> actually running quite slowly (~25MHz) inside. Contrast that with a design
> I've worked on with a 24MHz input clock; running logic at 150MHz and DRAM at
> 4-500MHz...

Thank you for helping my bad memory, Mark. I'd forgotten about
synthesizing faster clocks, was assuming the 50 MHz show on the
distributor's pages was the limit rather than the input. (It's what I
get for being to lazy to look up the specs for the part.)

Tell me, how possible would it be to have a 6809 with MMU implemented
in (reasonably cheap) FPGA running at 100+ MHz effective clock?

And how much power would it draw?

-- 
Joel Rees

One of these days I'll get someone to pay me
to design a language that combines the best of Forth and C.
Then I'll be able to leap wide instruction sets with a single #ifdef,
run faster than a speeding infinite loop with a #define,
and stop all integer size bugs with my bare cast.
http://defining-computers.blogspot.com/2017/06/reinventing-computers.html

More of my delusions:
http://reiisi.blogspot.com/2017/05/do-not-pay-modern-danegeld-ransomware.html
http://reiisi.blogspot.jp/p/novels-i-am-writing.html


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