[Coco] rgb2vga

[Mathieu Chouinard]

thanks. I will have to find another solution then

On Sun, Sep 25, 2016 at 1:45 PM, Cocodemus <retrocanada76 at gmail.com> wrote:
> It does not work with msx2, the signal keeps sinking. There is something on the vdp that cause this with the differential ports on altera.
>
> Sent from my iPhone
>
>> On Sep 25, 2016, at 6:58 AM, Mathieu Chouinard <chouimat at gmail.com> wrote:
>>
>> Hi,
>> Will an adaptation of the attached schematic
>> works for a commodore 128 or do I need to
>> go with the board modification ?
>> Also does any one as the cable schematic
>> for a MSX2+ (Sony HB-F1XDJ) ?
>> I can probably figure out the cable for
>> the atari 130xe (with a VBXE installed)
>>
>>
>> Mathieu
>>
>>> On Tue, Sep 20, 2016 at 11:23 AM, Mathieu Chouinard <chouimat at gmail.com> wrote:
>>> Hi Ed,
>>> thanks for the information.
>>> I managed to score a few nice things on ebay:
>>> 1 MSX2+, 1 Atari 130 XE, 1 Commodore 128 and 1 Ti-99/4A
>>> all still in the box ... hours of fun (and probably cursing too)
>>> at the horizion ...
>>> Mathieu
>>>
>>>> On Tue, Sep 20, 2016 at 11:19 AM, Zippster <zippster278 at gmail.com> wrote:
>>>> Hi Mathieu,
>>>>
>>>> R, G, and B are taken in on pins 1,2,3 as usual, composite sync on pin 13.
>>>>
>>>> Here’s the routing for the board I did (Luis’s original board has the same circuit).
>>>> <https://drive.google.com/open?id=0B1sgl615FlGnWmhISkRVZkRjU0k <https://drive.google.com/open?id=0B1sgl615FlGnWmhISkRVZkRjU0k>>
>>>>
>>>> As you can see, there’s no separate hsync and vsync on the connector, so for the
>>>> C128 RGB port, you would probably want to run some patches between the RGBI and
>>>> analog RGB connectors.  You’ll also need to patch the intensity line (with a voltage divider)
>>>> to the FPGA IO header as detailed on Luis’s site.
>>>>
>>>> An easier approach is probably to have one end of your cable a 10 pin header connection
>>>> and just use the analog port.
>>>>
>>>> A note of caution…  as you probably already know, the C128 will be putting out TTL level
>>>> signals, so you’ll want a series resistor on the RGB lines (to act as dividers with the already
>>>> present terminating resistors on the board) in order to drop the voltage to levels that won’t
>>>> harm the FPGA IO.  Also be sure you’re running with the ground fix on the hsync divider, for the
>>>> same reason.
>>>>
>>>> You may have to adjust the FPGA programming to sync the pixel clock with the one in the C128
>>>> more closely for the intensity signal to be applied to the video conversion in a stable manner.
>>>>
>>>> This issue could be avoided by using some logic and a simple resistor DAC to create pseudo-analog
>>>> signals from the TTL inputs before sampling.
>>>>
>>>> I hope that helps, and good luck.  :)
>>>>
>>>>
>>>> - Ed
>>>>
>>>>
>>>>
>>>>> On Sep 20, 2016, at 9:17 AM, Mathieu Chouinard <chouimat at gmail.com> wrote:
>>>>>
>>>>> On Tue, Sep 20, 2016 at 9:48 AM, Robert Gault <robert.gault at att.net> wrote:
>>>>>> Mathieu Chouinard wrote:
>>>>>>>
>>>>>>> what is the pinout of the rgbin connector?
>>>>>>> Mathieu
>>>>>>
>>>>>>
>>>>>> 9  7  5  3  1
>>>>>> .  .  .  .  .
>>>>>>
>>>>>> .  .  .  .  .
>>>>>> 10 8  6  4  2
>>>>>>
>>>>>> RGB pins on Coco3
>>>>> sorry I was talking about the DB15 RGBIN connector.
>>>>> I'm trying to build a cable for a commodore 128
>>>>>
>>>>> --
>>>>> A te quaeso, sicut in Aeneidos libro quarto Aeneas, elocutus
>>>>> desiderium erigendi suum obeliscum in templo Venereo Didonis, ab ea
>>>>> quaesivit, tuae domi an meae?
>>>>>
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>>>>
>>>>
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>>>
>>>
>>>
>>> --
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>>> desiderium erigendi suum obeliscum in templo Venereo Didonis, ab ea
>>> quaesivit, tuae domi an meae?
>>
>>
>>
>> --
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>> desiderium erigendi suum obeliscum in templo Venereo Didonis, ab ea
>> quaesivit, tuae domi an meae?
>> <pull2-rgba-xor.gif>
>>
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>
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-- 
A te quaeso, sicut in Aeneidos libro quarto Aeneas, elocutus
desiderium erigendi suum obeliscum in templo Venereo Didonis, ab ea
quaesivit, tuae domi an meae?