[Coco] Desired RESET behavior

[RETRO Innovations]

On 1/30/2016 11:18 PM, Theodore (Alex) Evans wrote:
>
>
> On 01/29/2016 10:27 PM, RETRO Innovations wrote:
>> I was able to speed up the SPI by using the awesome quadrature clocks of
>> the 6809.
>>
>> q ^ e generates a doublespeed clock, which means the SPI will operate at
>> 2X the normal clock.  Thus, a byte can be transferred in 4 E clock
>> periods.  I am not as familiar with the 6809 opcode timings, but I would
>> assume that most opcodes that can read/write $ffXX would take at least 4
>> clock periods.  Are there any that do not?
>
> Clock periods from when? 
Specifically, given an opcode like:

sta $ff5b

from the time the E clock goes low (marking the end of the current store 
instruction), what is the shortest amount of cycles needed to again 
access $ff5b?
> If you are talking about from the time the address is asserted on the 
> address bus. All of them do.  If you are talking the time from one 
> read to another, you can read into A or B in 4 cycles (or 3 on the 
> 6309) (LDA <$XX and LDB <$XX) 
So, 3 cycles.  In 3 E cycles, I can transfer 6 bits of data to the SPI.  
Any opcodes capable of again accessing $ff5b in 2 cycles?
> and D, U, or X in 5 cycles but this reads two successive bytes (LDD 
> <$XX).  If you are using a 6309 there are instructions which can read 
> from memory (as data) every other cycle while simultaneously writing 
> every other cycle.
Hmm, well, I guess 2 cycles it is.

I'll have to see if I can double the clock again.  I was not having much 
luck other day, but might find another option.  I hate to put a PLL on 
the board just to quadruple the clock.

Jim

>
>


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