dave at davebiz.com
Sat May 30 17:28:29 EDT 2015
Wow, that's a tall order. Maybe the FPGA itself could actually be made to do that....
On May 30, 2015 3:43 PM, Melanie and John Mark Mobley <johnmarkmelanie at gmail.com> wrote:
> We need a diagnostic test that will prove out the cycle acc
uracy timing of > the CPU so that it can be used to test the FPGA design. > > John Mark Mobley > > -- > Coco mailing list > Coco at maltedmedia.com > https://pairlist5.pair.net/mailman/listinfo/coco
More information about the Coco