[Coco] MPI Design

[RETRO Innovations]

I decided that a first step to understanding the Coco IO would be to 
design an MPI for at least my benefit, and maybe others.  I already make 
a simple version of the same thing for the Commodroe 64, and this seems 
doable.

I understand the $ff7f register, but looking at this schematic:

http://www.tandycoco.com/techdocs/26-3024-schem.jpg

I am curious on a few things:

  * U2 makes sense (buffer the data bus, no issues there, but I am
    curious why the output lines were buffered with 367s (U1,6,7,9)
    instead of octal 374s or 574s?
  * U3/U7/U4 creates the IO register, no concerns there
  * U14 allows the switch to drive the selections until a register is
    loaded has happened.  Cute.  Interesting that if one reads $ff7f
    before writing it, bits 2,3,6,7 seems to be undefined (probably read
    as 1 since the output pins of U4 are HiZ until ENREG is brought high...
  * U8 is address logic to derive the ENBUS, ENREAD, and LOADREG, but
    why an inverter on LOADREG?  The PAL could have done the inversion. 
    Does anyone know the equations?
  *   What is the difference in the PAL between Coco 1 and 2 and 3? I
    can't seem to relate these
    (http://www.coco3.com/community/2010/05/26-3124-mpi-coco-3-upgrade-1/)
    and (www.coco3.com/community/2010/06/26-3124-mpi-coco-3-upgrade-2/)
    to the schematic.  What is the patch doing, and why is it an
    either/or situation?
  * ON this page:
    http://www.gimechip.com/files/CoCo/Paul_Barton/CoCoZilla/mpi.html ,
    is there value in allowing someone to turn off the SCS and/or the
    CTS signals (bit 7 and 3 of $ff7f)?
  * Same page, why would there be value in putting the CART signal on
    pin 1 of the cart port?

My thought is to use the following:

'245 for databus buffer
3 '574s for address and other signal buffering  (replacing the 367s)
Xilinx XC9572XL-64 for the rest:

5 SCS lines
5 CART lines
5 CTS lines
4 switch inputs
8 bit databus
1 Q
1 E
1 SLEN
1 R/W
1 RESET
4 LED indicator lines
16 address lines

Is there value in doing a 6 or 8 or larger MPI?  It's trivial to do, but 
the IO above takes up all of a 9572 IO, and each additional slot takes 1 
SCS, 1 CART, 1 CTS, 1 switch line, and 1 LED line (5 lines), so if the 
design should handle 6 or 8 slots, I need to cut down on the number of 
address lines coming in (maybe restrict it to 8 and use the MPI trick of 
leveraging a '30 to grab address lines 8-15 when high.

Also, any source for the PCB mount 20/40 connectors?

Jim



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