[Coco] Altera DE1 - CoCo3FPGA suggestions

[Mark McDougall]

On 21/02/2014 10:27 PM, tim at franklinlabs.com wrote:

> I plan on using the SRAM for the video and the DRAM for the CPU. The CPU
> to Video data transfer fix still needs some work and testing but it
> involves a FPGA RAM FIFO controller.

All my early designs used dual-port on-chip RAM for video memory. Of course 
that restricts the platforms, but most early arcade systems only had very 
small video memory footprints. The beauty is that you can drive any 
resolution at any clock rate without touching the rest of the design.

Most computer systems had larger video memory footprints and even allowed 
them to be situated anywhere in RAM, and interleaved CPU and video accesses 
with varying degrees of... finesse. Not suitable for on-chip dual-port RAM 
except in larger FPGA devices unfortunately.

For video it's possible to burst into a FIFO as long as you can pre-empt it 
and maintain CPU access timings without unwanted wait-states (unless you 
want to get really tricky, and let the CPU 'catch up', which is possible). 
I've done that (the FIFO idea) with a NIOS-based design onto which I ported 
(chocolate) DOOM - though of course there was no hard CPU access 
requirements in this case, as there would be when emulating a cycle-accurate 
Coco. Worked quite well in the end.

> That's a new resource for me. I'm going to check it out. Thanks!!!

He hasn't released his Replay source AFAIK yet; I've seen developments such 
as the aforementioned discussed on the Replay forums. IIUC he will be 
releasing it, but not when I don't know.

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"