[Coco] Multi-Processor 6809 Computer System

[Mark McDougall]

On 1/05/2013 11:34 PM, Luis Antoniosi (CoCoDemus) wrote:

> Not a computer engineer expert but IFAIK only scalar architectures can
> achieve 1 cycle per instruction by pre-fetching and pipelining instructions
> and predicting branches. But on a coco machine what would be smaller cycle
> count ? 4 cycles ?

With all due respect, I think we're starting to get into the realms of 
pipe-dreams (no pun intended) here.

My colleague & I have started work on a cycle-accurate 6309 core; I can't 
even fathom attempting a pipelined version with or without branch 
prediction. And trying to implement pipelining on a CPU with 
read-modify-write instructions would be a nightmare! :O

Realistically, IMHO, the only incarnation we'll ever see of a Coco running 
at upwards of 20MHz is going to be in an FPGA... forget trying to replace 
the CPU on a Coco motherboard if you want a significant speed boost.

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"