[Coco] 6309/6809 opcodes with mixed 8/16 bit registers

[jdaggett at gate.net]

On 22 Nov 2012 at 12:36, Harry Hurst wrote:

> I've heard about the RESET. I've never tried it. There appear to be 3
> HCF's on the 6809, opcodes $14, $15, and $CD. I've tried all of those
> and
> their page $10 and $11 counterparts. They all work.
> 
> Go to this page:
> https://sites.google.com/a/aaronwolfe.com/cococoding/home/docs
> 
> Download the "6x09_Instruction_Sets.pdf" there. It has all of this and
> more, and it's laid very neatly.
> 
> Thanks,
> HH

Since the 6800's HCF opcode is $DD, I would suspect that the 6809 could be $CD. This 
would force into a test mode in which the address bus becomes essentially a 16 bit counter. 
In the 6800 the HCF mode does not do a fetch cycle. So it takes a hard reset or power on 
reset to get it out of that test mode. Opcodes $14 and $15 may do other internal test that one 
would have to have a logic analyzer on the pins to determine more what they do. 

The internal workings of the 6809 determine instruction and addressing mode from a one 
byte opcode. The often called prebyte is actually a page switch byte or instruction modifier 
byte. The upper nibble of the opcode determines addressing mode with the exception of $1 
and $3. Take for expample Indexed mode. The upper nibble for indexed mode are $6, $A 
and $E. 

here is a better look at the bits individually

$6	0110
$A	1010
$E	1110

Only the two MSbits change so that to decode indexed addressing mode you only need an 
equation of 

(bit3 or bit2) and bit1 and not(bit0)

This yeilds a two bit OR gate and an inverter and a three bit AND gate. 

All the decode logic is done essentially the same way. There is no microcode. Thus the 
speed limitation of this type design is based on the geometery of the gates and the 
propogation through the gates. The page switch byte or instruction modifier byte will alter the 
instruction and/or the destination register. This can be seen in page one opcodes $8C, $9C, 
$AC and $BC. These are all CMPX in four addressing modes. Add the page switch byte in 
front of the above opcodes and the register acted on goes from X to Y. Similarly the page two 
byte changes the register acted on to S. This is essentially the heart of the patent that is 
called the Instruction Set Modifier Register. The instruction modifier byte is loaded first and 
then the output of the register is fed to the decode logic to alter the instruction and/or the 
register acted on. 

Depending on how complete the decode of the unused opcodes are they will do something or 
do nothing. That is the one fault of the 6809. It would have been nice if they funneled them 
into a fault vector. Looking at the vector map there seemed to be intended 16 pairs of bytes 
for the vector table originally. Only 7 were ever implemented. Hitachi in the 6309 did 
implement the fault vector.  A wise move on their part. 

just giving a bit of insight on my opinion of how the beloved processor works. Much of it 
comes from working with the sister of the 6809, the HC11. Also I did and extensive patent 
search several years ago and downloaded a few. Also I gleened some info from the Byte 
magizine article that describes some of the work done on the processor. By far I am no 
expert or claim to be. I found that it was an interesting design and having worked for Motorola 
for 23yrs, it was neat to try and figure out how the actual circuit design was done. It was a 
remarkable design that probably greyed a few engineers hair back then. To do that complex 
of a circuit with no modern tools to simulate and verify the design is a chore. Even 
breadboading the IC itself had to be labor intensive project if that was done. 

james