[Coco] A Technical Question

[John Kent]

On 19/05/2012 5:20 AM, jdaggett at gate.net wrote:
> On 18 May 2012 at 16:03, Mark McDougall wrote:
>
>> 2. HALT CPU access to video memory during active video. Obviously
>> detrimental to CPU performance.
> Definitely a poor way to go if you have constant and/or frequent IRQs. If the HALT period is
> long enough to overlap two or more IRQs then the first is latched and subsequent IRQs will
> more than likely be lost.
>
> HALT is a nice way for a peripheral processor to use the commonmemory for short burst say
> about 32 bytes or less. The 6809 version, not 6809E, with its internal DMA module only
> allows up to 32 cycles before another cpu cycle is ran. With two cycles per byte would mean
> 16 bytes per DMA cycle max.
>
>
> james

When the CoCo accesses RAM on alternative clock phases, you are 
effectively only using half the memory bandwidth. If you are using 640 x 
480 pixel VGA format with 8 bit color then you need a byte access you 
need a byte access every 40nsec. Since the CoCo doesn't support that 
sort of graphics resolution access to memory can be significantly 
reduced. If you are using 600nsec access memory multiplexed between the 
CPU & video and you are using 16KHz line scan rate  and 256 x 192 x 2 
colours then you probably are accessing memory at 1.2 usec / byte which 
is pretty much half the memory bandwidth. With an FPGA Coco though 
running VGA  clock rates (32KHz line rate) you have to access memory 
every 600nsec but with 40nsec memory you only need to access a byte 
every 15 or 16 CPU cycles, which is not a big overhead on the CPU 
inserting wait states. If the video does not require the full memory 
bandwidth then it probably is more efficient to steal cycles from the 
CPU assuming the CPU is taking advantage of the full memory bandwidth.

I was looking at the spec sheet for the 6844 DMA controller and that 
seemed to release the bus for 1 cycle in 14, if it has continuous bus 
access, hence preventing the CPU from being completely blocked during 
large DMA transfers. The registers in NMOS are dynamic, but I'm not sure 
if Halt necessarily prevents the dynamic registers from being refreshed. 
It might. I'm not sure.

John.

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