[Coco] A Technical Question

[T. Franklin]

I have atechnical question about the video link and RAM on a computer (not necessarilya CoCo). I'm creating my own 6809 basedcomputer on an FPGA and stuck on a direction as to implementation. It has to dowith the write CPU cycle of the video area. Is it normal to allow the CPU towrite to video RAM only during the refresh & blanking? If so, is it normalto use a dual port RAM scheme or is the processor held in a wait state until thehorizontal scan is complete? 

Some of theideas I had with this venture is to (like others) implement a CoCoin an FPGA but modify all the graphics routines (i.e. lines, circles, draws andPCLS) to all FPGA core implementation. I?m thinking about adding a 3D FPGA coreimplementation similar to OpenGL for some real cool CoCogaming.
This is just mydream but as I slowly get started, I?m finding that questions like this oneplague me for weeks. So any help would be appreciated. 

See you all atCoCoFest!!!