[Coco] 6809 / General CPU question

[Lothan]

This is from Color Basic Unraveled given the the SAM redirects $FFF0-$FFFF 
to $BFF0-$BFFF:

LBFF0  FDB  LA681    RESERVED
LBFF2  FDB  SW3VEC   SWI3
LBFF4  FDB  SW2VEC   SWI2
LBFF6  FDB  FRQVEC   FIRQ
LBFF8  FDB  IRQVEC   IRQ
LBFFA  FDB  SWIVEC   SWI
LBFFC  FDB  NMIVEC   NMI
LBFFE  FDB  RESVEV   RESET

RESVEC LEAY LA00E,PC POINT Y TO WARM START CHECK CODE
LA02A  LDX  #PIA1    POINT X TO PIA1
       CLR  -3,X     CLEAR PIA0 CONTROL REGISTER A
       CLR  -1,X     CLEAR PIA0 CONTROL REGISTER B
       CLR  -4,X     SET PIA0 SIDE A TO INPUT
       LDD  #$FF34   *
       STA  -2,X     * SET PIA0 SIDE B TO OUTPUT
       STB  -3,X     * ENABLE PIA0 PERIPHERAL REGISTERS, DISABLE PIA0
       STB  -1,X     * MPU INTERRUPTS, SET CA2, CA1 TO OUTPUTS
       CLR  1,X      CLEAR CONTROL REGISTER A ON PIA1
       CLR  3,X      CLEAR CONTROL REGISTER B ON PIA1
       DECA          A REG NOW HAS $FE
       STA  ,X       BITS 1-7 ARE OUTPUTS, BIT 0 IS INPUT ON PIA1 SIDE A
       LDA  #$F8     =
       STA  2,X      = BITS 0-2 ARE INPUTS, BITS 3-7 ARE OUTPUTS ON B SIDE
       STB  1,X      * ENABLE PERIPHERAL REGISTERS, DISABLE PIA1 MPU
       STB  3,X      * INTERRUPTS AND SET CA2, CB2 AS OUTPUTS
       CLR  2,X      SET 6847 MODE TO ALPHA-NUMERIC
       LDB  #$02     *
       STB  ,X       * MAKE RS232 OUTPUT MARKING
       LDU  #SAMREG  SAM CONTROL REGISTER ADDR
       LDB  #16      16 SAM CONTROL REGISTER BITS
LA056  STA  ,U++     ZERO OUT SAM CONTROL REGISTER BIT
       DECB          * DECREMENT COUNTER AND
       BNE  LA056    * BRANCH IF NOT DONE
       STA  SAMREG+9 SET DISPLAY PAGE AT $400
       TFR  B,DP     SET DIRECT PAGE TO ZERO
       LDB  #$04     USE AS A MASK TO CHECK RAMSZ INPUT
       STA  -2,X     SET RAMSZ STROBE HIGH
       BITB 2,X      CHECK RAMSZ INPUT
       BEQ  LA072    BRANCH IF JUMPER SET FOR 4K RAMS
       CLR  -2,X     SET RAMSZ STROBE LOW
       BITB 2,X      CHECK RAMSZ INPUT
       BEQ  LA070    BRANCH IF JUMPER SET FOR 64K RAMS
       LEAU -2,U     ADJUST POINTER TO SET SAM FOR 16K RAMS
LA070  STA  -3,U     PROGRAM SAM FOR 16K OR 64K RAMS
LA072  JMP  ,Y       GO DO A WARM OR COLD START



-----Original Message----- 
From: Stephen H. Fischer
Sent: Saturday, February 19, 2011 11:23 PM
To: CoCoList for Color Computer Enthusiasts
Subject: Re: [Coco] 6809 / General CPU question

Hi,

One more try.

When a computer using a 6x0x CPU is turned on, a read is done from FFFF and
FFFE.

By some means this read must come from ROM.

So the address in FFFE and FFFF that the hardware reads from is what is
programmed into the ROM.

--------------------------
ORG $A000
..
ROM program code
..

ORG $BFFE

The 8 low order bits of the reset address
The 8 high order bits of the reset address

End of ROM
--------------------------

Or does the 6809 have them reversed, I forget.

As I said before, the CPU in the CoCo 2 gets the contents of memory
locations FFFE and FFFF from BFFE and BFFF. As does the CoCo 3.

SHF

----- Original Message ----- 
From: "Mike Rowen" <mike at bcmr3.net>
To: "CoCoList for Color Computer Enthusiasts" <coco at maltedmedia.com>
Sent: Saturday, February 19, 2011 7:46 PM
Subject: Re: [Coco] 6809 / General CPU question


> Well, so far I think that everyone is in agreement that when the 6809 is
> powered on, it loads the address stored at FFFE & FFFF into the program
> counter, thus pointing it to the first instruction to be executed. While
> the
> CoCo is one model to reference, it still leaves the original question. How
> does a memory address get into these locations, CoCo or otherwise? All
> 6809
> based systems that I've looked up, appear to load the initial PC register
> with these bytes at these locations. So it appears that is part of the
> internal 6809 architecture. While I find lots of references to the FFFE &
> FFFF addresses, still nothing to indicate how these addresses are
> populated
> with the bytes of the first address. Since every machine does not have 64k
> installed, it seems to me that these addresses are reserved and masked in
> hardware somehow. If someone were designing a 6809 computer, they would
> have
> to know how this works and how to do it. :)
>
> -Mike
>
>
> On Sat, Feb 19, 2011 at 10:24 PM, Darren A <mechacoco at gmail.com> wrote:
>
>> On 2/19/11, Stephen H. Fischer wrote:
>> >
>> > The CoCo 2 manual says "if the CPU reads FFFF it will actually read the
>> > contents of BFFF".
>> >
>> > If the ROM is switched out will BFFF come from RAM?
>> >
>> ---
>>
>> Yes and no.  If the SAM is put in ALL RAM mode then reading directly
>> from BFFE and BFFF will read the RAM (assuming the CoCo has 64K RAM).
>> But when the CPU reads from FFFE and FFFF, the SAM will always output
>> a device code to select the ROM.  So the RESET vector (and all
>> Interrupt vectors) are always read from ROM even when the CoCo is in
>> ALL RAM mode.
>>
>> A cartridge can override the internal Reset and Interrupt vectors by
>> decoding those addresses and asserting SLENB* to prevent selection of
>> the internal ROM.
>>
>> Darren
>>
>> --
>> Coco mailing list
>> Coco at maltedmedia.com
>> http://five.pairlist.net/mailman/listinfo/coco
>>
>
> --
> Coco mailing list
> Coco at maltedmedia.com
> http://five.pairlist.net/mailman/listinfo/coco


--
Coco mailing list
Coco at maltedmedia.com
http://five.pairlist.net/mailman/listinfo/coco