[Coco] 6809 / General CPU question

Steve Bjork 6809er at srbsoftware.com
Sat Feb 19 11:43:41 EST 2011

In the era of the 6809, it was up to the circuit designer to hold the 
reset line of the CPU low till the system was stable. Not only did the 
power have to be stable but the other chips and circuits need to ready 
for the CPU to do its work.

Some CPUs would just start running at address zero but the 68XX type of 
chips would use the Reset Vector (store at address $FFFF) as the 
location to start with.  The 6809 would also turns off its ability to 
service interrupts so the hardware and RAM can be initialize so the 
system will run correctly.

The 6809 was design that the RESET line as cold (power on) reset.  The 
CoCo design takes this one step further by using the Reset Line as both 
cold and warm reset.  Since the memory is fill with random  data with 
power on (cold) reset code looks at a byte in memory to decide if it 
should do a cold or warm restart.  If byte at $71 hold the value of $55 
then it will attempt a warm reset else it will do a cold reset 
initialize the computer's memory with all the stuff needed for BASIC to run.

As I said, the reset code will attempt a warm start. The next step is 
for the code to grab the warm reset vector at $72.  But before the code 
starts at the new address, it must make sure the code starts with a NOP 
($12) instruction to verify this is good code and the vector is not 
pointing to random address.

The bottom line is the CoCo always does a power on reset whenever the 
Reset Line is activated, be it power on or someone hitting the reset 
button.  Its the power-up/reset code and the status of $71 (Reset Flag) 
/ $72 (Vector address) controls what it should do.

Steve (Zaxxon) Bjork

On 2/19/2011 4:59 AM, Mike Rowen wrote:
> Basic theory question here. When a 6809 is powered up, does it automatically
> begin fetching instructions at a specific location? I have been looking
> through some books, but I have yet to find any document that describes the
> boot process from the CPU perspective.
> Regards,
> -Mike
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