[Coco] COCO FPGA

[Joel Ewy]

On 12/22/2011 10:56 AM, Tony Cappellini wrote:
> I think the two new coco projects (I forgot the actual names though) are
> quite an accomplishment, and hope to get one myself.
> One limiting factor on these is not having the expansion port. Does anyone
> know if either of these projects intends to add the coco expansion
> port - or better yet- build an MPI right into one of these boards?
>
>
> Thanks
>

I'm not quite sure which two projects you are referring to.  Gary 
Becker's project is called CoCo3FPGA, and it is available right now.  It 
works with two different FPGA development boards:  the Digilent Spartan 
3, and the Altera DE1.  I believe that James Daggett  has done some work 
on implementing the GIME functionality in an FPGA, and Mark McDougall 
has implemented a CoCo 1/2 on an FPGA board, but I'm not aware of either 
of these having released code, or being available in any other form yet.

CoCo3FPGA uses off-the-shelf FPGA development boards, which makes it 
pretty affordable, but means that you have to work with what you get.  
On the Spartan 3 board, you need to add a VGA breakout board with some 
resistors because the built-in VGA port offers only 1 bit of color per 
R,G,B.  You also need to build an expansion board if you want to hook up 
joysticks.  I don't think there is an option for the 40-pin expansion 
bus yet.

Here's what the release notes from the latest version says about the 
current MPI implementation:

"MPI Slots

The MPI slots have been redefined in this version. The MPI switch is set 
using two of the S3 board slide switches.

Slot 4 contains the Disk BASIC ROM.
Slot three contains a multiple cartridge ROM system designed by John at 
gimechip.com. The IO locations for slot 3 are used to select the ROM 
bank from SRAM.

$FF40 - The lower three bits sets the ROM bank. The same location used 
by the super program paks to bank the 16K of the Pak ROM at a time. The 
ROM banks are written into the SRAM every 32K. This
allows the super program paks to function, but wastes 16K per bank. A 
method of recovering this 16K is explained below. But by using the 
larger addressing spacing, it allows program paks that are the maximum 
allowable 32K. This location is set to 0 by a system reset.

$FF41 - Not yet implementated.

$FF42 - BANK 0 Flash ROM address. The 2 Meg Flash ROM allows for up to 
sixty four 32K ROMs. By setting this location to a value between 0-63, 
the upper six address bits for the Flash ROM are set when location $FF40 
is set to 0. This location is not cleared with a RESET.

$FF43 - Bank Size latch. Only two bits used.
Bit 0 sets the bank size
0 32K bank size
1 16K bank size
If the CoCo3 is set for a 32K ROM, the 16K bank will be aliased to the 
32K size.
Bit 1 is used only if Bit 0 is set to 16K. To recover the unused 16K of 
the 32K Flash address
spacing, two 16K program ROMs can occupy a 32K Flash space.
0 Use lower 16K of each 32K Flash space
1 Use upper 16K of each 32K Flash space

$FF44-$FF4A Bank 1through Bank 7 Flash ROM address. Same as $FF42, 
except for banks 1-7
The eight 16K banks allows up to 128K ROMs. Software needs to be written 
that reads Pak ROMs over DriveWire and stores them into SRAM. If there 
is enough FPGA block RAM, the software could be stores in the FPGA. If 
not, a standalone program can be loaded from Disk."

JCE

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