[Coco] 6x09 read and write strobes.

[jdaggett at gate.net]

John

The circuit that I described is off the SIMON6809 board. It is used to access external RAM 
and EEPROM. The ram is a 32K  and the EEProm is a 2865 8K part. 

The MC6800, 6801,6802, 6805, 6809 and 6811 all use the faling edge of the E-Clock to start 
the machine cycle. All hae internal clocks that are out of phase from the E-clock. It is a bit 
confusing to state which clock leads whom. It is all a matter of where you call the starting 
point for a machine cycle. For the 6809 the Q-Clock is used for internal along with, I believe, 
an inverted E-clock if Iread the schematic of the 6800 correctly. The 6809 used the same 
basic archetecture as the 6800. They reprogrammed the internal PLA for different 
instructions and added some other circuits. One was an Intruction Set Modify Register for 
which there is a patent for that. The opcodes $10 and $11 affectionately called pre-bytes 
actually modify the opcode following by changing the output of the PLA in the intruction set 
decode logic. The other main circuit added was the Fast Interupt Circuit. Again a patent was 
awarded for that. That gave the 6809 the FIRQ, a second interrupt source. 

The Motorola processors used the rising edge of the E-Clock to tell the peripherals that it was 
using the bus. In the COCO that is why the video acceses ram while the E-clock is low. 
Peripherals can then be interleaved with the CPU clock cycles. The positive E-clock acts as 
an enable. This is opposite polarity of the Intel system. 

james

On 16 Dec 2011 at 14:38, John Kent wrote:

> Falling edge of Q is it ?
> I posted a timing diagram, on 2011/12/05 but I must have had Q inverted.
> 
> You can use a 7400 to generate read and write strobes, or half a 74139 
> decoder.
> Phil was using a CPLD and verilog to program it.
> The equations he used were:
> 
> assign RD            = E & RW & Reset;
> assign WR            = Q & ~RW & Reset;
> assign nRD            = ~RD;
> assign nWR            = ~WR | RamWP;
> 
> what it should have been I think was:
> 
> assign RD            = E & RW & nReset;
> assign WR            = E & ~RW & nReset;
> assign nRD            = ~RD;
> assign nWR            = ~WR | RamWP;
> 
> I'm not sure if his reset was active high or active low.
> I have not used verilog much, so I'm not 100% sure of the syntax.
> Some peripherals such as the Z8530 assert both RD & WR to reset the 
> peripheral, if my memory serves me correctly. I'm not sure if Phil was 
> trying to do that or if he was trying to prevent random read/writes 
> during reset.
> 
> I didn't get a reply from Phil Harvey-Smith, so I'm not sure if he has 
> sorted out his problem.
> 
> John.
> 
> 
> On 16/12/2011 1:13 PM, jdaggett at gate.net wrote:
> > Phil
> >
> > Not sure if this is too late or not.
> >
> > The 6809 use the E clock to primarily sync with peripherals as well as internal uses. The Q
> > clock is an internal clock. The address bus as well as the RW line are all valid on the falling
> > edge of the Qclock after the falling edge of the Eclock. The falling edge of the Eclock starts a
> > new cycle. You can generate an Intel compatible Write enable output by inverting the RW line
> > and NANDing it with the Eclock.  A comparable Output Enable read signal is just NANDing
> > the RW line with the E clock.
> >
> >
> > james
> >
> 
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