[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Fedor Steeman]

Whoah! Heavy stuff! Thanks everyone for the detailed explanations. It really
nailed it for me this time. I don't think there is any more room for
confusion. I really get it now. Much obliged!

I actually have a background as a biologist, but the past decade or so I
have morphed into ICT. Thanks to my childhood experience with the CoCo,
where I did a lot of programming in BASIC, this was relatively easy for me.
Now I am determined to get to the bottom and understanding this little
mystery machine from my childhood.

Cheers,
Fedor

On 25 May 2010 02:17, <jdaggett at gate.net> wrote:

> Fedor
>
> First off you have a rounding error in that you are not using enough
> decimal spaces.
>
> On the Coco 1 and 2 the SAM chip divides the 14.318181 MHz crystal by 16 in
> slow mode
> and 8 infst mode to produce the E and Q clocks.  That period is roughly
> 1117nS for slow
> mode. The duty cycle for the E and Q clocks is a minimum of 45% and a
> maximum of 55%.
> That includes rise and fall times. There is a spec for the jitter cause by
> generating the
> quadrature phase shift of the E and Q clocks.
>
> Each clock, E and Q are both the same period. The phase difference does not
> have to be
> exactly 90 degrees. I believe is can vary by about plus or minus 10 degrees
> and the
> processor will work fine.
>
> Also you can think of the quadrature clock as having four states per cycle.
>
> eclock qclock   state
>   0          0           0
>   0          1           1
>   1          1           2
>   1          0           3
>
> The SAM chip much of the timing is generated off the 14.318 MHz clock. Each
> state is the
> basically 4 clock periods of the 14.318 MHz clock (~279nS). Data to and
> from the MPU
> nevers passes through the SAM chip. Only the address buss does.
>
> >
> > E-low & Q-low: SAM sets RAM address for VDG (State 0)
> >
>
> Correct.
>
> >
> > E-low & Q-high: VDG reads data byte (State 1)
> >
>
> Correct
>
> >
> > E-high & Q-high:  CPU sets RAM address (State2)
> >
>
> Correct
>
> >
> > E-high & Q-low: CPU reads/writes RAM byte(State3)
> >
>
> The MPU writes data during this state. MPU reads actually occur at the end
> of this state
> when the Eclock falls to start the next state which is State0. Per the 6809
> data sheet the data
> buss is larched in on the falling edge of the Eclock which also starts the
> next machine cycle.
>
> hope this helps.
>
> james
>
>
>
>
> On 24 May 2010 at 21:49, Fedor Steeman wrote:
>
> >
> > Another thing about this clock cycle I cannot seem to figure out is the
> > duration. How long does one clock cycle take?
> >
> > As the 6809 (normally) operates at 0.89 MHz, I can calculate the duration
> > of
> > a single E-clock wave (i.e. rise and fall), ought to be 1124
> > nanoseconds.
> >
> > According to the reference manual, however, the duration is apparantly
> > 1117
> > nanoseconds:
>
>
>
>
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