[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Lothan]

Look at the drawing closer and you'll see that the low time for the E clock 
is 629 ns and the high time for the E clock is 488 ns. The edges of the E 
clock are not accounted for in the timing relationship so it's pretty easy 
to deduce this is likely where you'll find the missing 7 ns.

--------------------------------------------------
From: "Fedor Steeman" <petrander at gmail.com>
Sent: Monday, May 24, 2010 3:49 PM
To: "CoCoList for Color Computer Enthusiasts" <coco at maltedmedia.com>
Subject: Re: [Coco] CoCo 1&2 clock cycle events (CPU, SAM,VDG interaction 
with RAM)

> Hi all,
>
> Another thing about this clock cycle I cannot seem to figure out is the
> duration. How long does one clock cycle take?
>
> As the 6809 (normally) operates at 0.89 MHz, I can calculate the duration 
> of
> a single E-clock wave (i.e. rise and fall), ought to be 1124 nanoseconds.
>
> According to the reference manual, however, the duration is apparantly 
> 1117
> nanoseconds:
>
> http://www.bighole.nl/pub/mirror/homepage.ntlworld.com/kryten_droid/coco/coco_tm_18.png
> (actually there is a typo, as it says '117')
>
> I really cannot make sense of this diagram, as there are two other 
> numbers,
> 629 ns og 488 ns, that add up to 1117, but there start and end points seem
> to drawn wrongly.
>
> Does this mean that the low section of the E clock has a shorter duration
> (488 ns) than the high section? And where are the missing 7 nanoseconds
> (1124 - 1117) ?
>
> I am pretty much confused.
>
> I just want to know who long this cycle takes and each of its steps:
>
>        E-low & Q-low: SAM sets RAM address for VDG
>        E-low & Q-high: VDG reads data byte
>        E-high & Q-high:  CPU sets RAM address
>        E-high & Q-low: CPU reads/writes RAM byte
>
> Thanks for any help...
>
> Cheers,
> Fedor
>
>
> On 21 May 2010 20:58, Fedor Steeman <petrander at gmail.com> wrote:
>
>> Awesome! So simply put (and I am sorry for oversimplifying), this is wat 
>> my
>> little sequence of events should look like:
>>
>>         E-low & Q-low: SAM sets RAM address for VDG
>>         E-low & Q-high: VDG reads data byte
>>         E-high & Q-high:  CPU sets RAM address
>>         E-high & Q-low: CPU reads/writes RAM byte
>>
>> Right? Thnx for helping out!
>>
>> Cheers,
>> Fedor
>>
>>
>>
>> On 21 May 2010 16:26, Darren A <mechacoco at gmail.com> wrote:
>>
>>> On 5/21/10, Fedor Steeman wrote:
>>> > Hi all,
>>> >
>>> > Looking in the Technical Ref Manual, studying the diagrams, and 
>>> > several
>>> > other sources on the internet, I am trying to understand exactly the
>>> > sequences of events during a CoCo 1/2's clock cycles. As I am not an
>>> > electronics buff, this is not an easy task for me. I just wanted to 
>>> > know
>>> in
>>> > what order, CPU, and VDG interact with RAM, as mediated by the 
>>> > clocking
>>> > signals provided by the SAM.
>>> >
>>>
>>> ---
>>>
>>> This is my understanding.  Someone please correct me if I'm wrong:
>>>
>>> The CPU presents a stable address from the rising edge of Q to the
>>> falling edge of E.  The CPU's data window is in the latter portion of
>>> E High. Data is latched by the CPU on the falling edge of E.
>>>
>>> The SAM is responsible for addressing RAM using either the CPU address
>>> or its own internal video offset counter.  It (roughly) presents the
>>> CPU address after E goes High and the VDG address after E goes Low.
>>> The VDG reads RAM during the latter portion of E Low.
>>>
>>> Darren
>>>
>>> --
>>> Coco mailing list
>>> Coco at maltedmedia.com
>>> http://five.pairlist.net/mailman/listinfo/coco
>>>
>>
>>
>
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