[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Fedor Steeman]

Awesome! So simply put (and I am sorry for oversimplifying), this is wat my
little sequence of events should look like:

        E-low & Q-low: SAM sets RAM address for VDG
        E-low & Q-high: VDG reads data byte
        E-high & Q-high:  CPU sets RAM address
        E-high & Q-low: CPU reads/writes RAM byte

Right? Thnx for helping out!

Cheers,
Fedor


On 21 May 2010 16:26, Darren A <mechacoco at gmail.com> wrote:

> On 5/21/10, Fedor Steeman wrote:
> > Hi all,
> >
> > Looking in the Technical Ref Manual, studying the diagrams, and several
> > other sources on the internet, I am trying to understand exactly the
> > sequences of events during a CoCo 1/2's clock cycles. As I am not an
> > electronics buff, this is not an easy task for me. I just wanted to know
> in
> > what order, CPU, and VDG interact with RAM, as mediated by the clocking
> > signals provided by the SAM.
> >
>
> ---
>
> This is my understanding.  Someone please correct me if I'm wrong:
>
> The CPU presents a stable address from the rising edge of Q to the
> falling edge of E.  The CPU's data window is in the latter portion of
> E High. Data is latched by the CPU on the falling edge of E.
>
> The SAM is responsible for addressing RAM using either the CPU address
> or its own internal video offset counter.  It (roughly) presents the
> CPU address after E goes High and the VDG address after E goes Low.
> The VDG reads RAM during the latter portion of E Low.
>
> Darren
>
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