[Coco] Interesting reading

[jdaggett at gate.net]

On 19 Jun 2010 at 22:34, Darren A wrote:

> I agree that is probably the latter.  The reponse to an IRQ or FIRQ
> cannot occur until after the current instruction has completed.  If
> the current instruction were an SWI, its completion would include
> setting the I and F masks. This would prevent the CPU from responding
> to the IRQ or FIRQ before the SWI.
> 
> Darren

Darren

Looking at the circuit that is included in the patent it soes look as if thhre is inhibits to prevent 
any maskable IRQ as long as a CWAI or SWI is being serviced.

Part of the priority network inputs is the I and F bits from the CCR. If any of these are set then 
a low on the IRQ or FIRQ pins is essentially ignored. IF my memory serves me correct the 
SYNC, SWI2 and SWI3 do not set the I bit and/or F bit.

My deduction fromteh flow chart that is included in the patent as well as the programming 
manual, the external inputs are processed prior to fetch of an opcode in each cycle. From 
this crazy circuit it looks as if they "NOR" the three interrupts( NMI, FIRQ, IRQ) to form one 
signal to the control logic. The NMI and IRQ are resolved somehow but if the E bit in the CCR 
is not set then that indicates a FIRQ has occurred. The output of the NMI and IRQ latches 
drives a set/reset latch the goes to the E bit of the CCR. The FIRQ latch resets that latch. 

My best guess is that if the E bit is set and the I and/or F bit is clear then the processor 
knows it is a NMI. If the E bit is set and the I bit is set then it is an IRQ. If the E bit is clear and 
the F bit is set then it is a FIRQ. SO there needs to be, and is, means to prevent the F bit 
being set while the E and the I bit are set. That seems essentially how the priority network 
works. 

james