[Coco] Assembler Question???

jdaggett at gate.net jdaggett at gate.net
Wed Sep 2 13:27:10 EDT 2009

On 2 Sep 2009 at 13:00, Robert Gault wrote:

> jdaggett at gate.net wrote:
> > To the list:
> > 
> > I have started looking at two FPGA cores for the 6809 in altering one of them to handle 
> > 6309 opcodes and stumbled across a potential  issue. As far as I can remember the 
> > Motorola Freeware Assemblers treat subtraction as adding the 2's compliment of the 
> > subtrahend. Also I seem to remember that is how the internal workings of the MC6809 
> > is. There is actually no subtractor but the assemly code has the 2's compliment of the 
> > subtrahend and does addition. 
> > 
> > If this is so then, the ALU becomes simpler when doing a FPGA core.
> > 
> > james 
> > 
> Can't find anything regarding the guts of the 6809 or 6309 in the data 
> sheets with respect to how subtraction is accomplished. Assembly code 
> can use either SUBA #-1 or ADDA #$FF to get the same answer but that 
> does not indicate what happens in the CPU core.


That is what I would expect. To better qualify what my question better is what is the 
binary code generated from a SUBA #1. My suspicion is;

When SUBA #1 ( immedate mode)  is assembled and it is stored in binary form as

$80 $FF instead of $80 $01. 

Why I think this is because of the two things. One from what I remember  from teh 
MC6800 schematic, there was an internal adder but no subtractor. Subtraction was done 
by 2's compliment. Also by the branch relative instruction offset byte(s) are stored as 2's 
compliment so that a simple add is performed and the adition is unsigned addition.

Also the Motorola Freeware Assembler mentions that arithmetic is done is 2's 
complement.  Thus this implies that subtraction is done with 2's complement. 

I can be wrong about this and to do addition internally, one port to the ALU has a 2's 
complement generator at its input to do subtraction by addition

Any way I can implement a 2's complementor and then do add and either invoke it or 


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