[Coco] SVGA monitor

jdaggett at gate.net jdaggett at gate.net
Sat Oct 17 10:58:34 EDT 2009

On 17 Oct 2009 at 0:32, Gene Heskett wrote:

> On Saturday 17 October 2009, RJRTTY at aol.com wrote:
> >In a message dated 10/16/2009 4:12:33 P.M.  Eastern Daylight Time,
> >msmcdoug at iinet.net.au writes:
> >
> >RJRTTY at aol.com  wrote:
> >>> It does but all that is internal in the AL250  scan
> >>> doubler chip.   It handles NTSC and PAL and  my
> >>> converter can use either mode....
> >>
> >>Well I'm confused  then. How do you get a 60Hz frame rate from a 50Hz
> >
> >source
> >
> >>with only a  line doubler???
> >>
> >>Regards,
> >
> >I have no idea.  :)   I just assemble the components  and
> >they do the work.   I do know that the output for the
> >PAL mode is cleaner than for NTSC.   Don't know
> >why that happens either.   Perhaps it is because the
> >PAL signal is generated outside the GIME chip.
> >
> >Roy
> >
> Entirely possible Roy.  The only 87 gime I have has extremely puny output 
> drivers in its RGB circuitry, with rise & fall times in the 350ns area.  Not 
> to mention a visible noise level from the 14 mhz clocking on my 100mhz scope.  
> Short of jacking up the vcc, which may blow a chip made out of pure 
> unobtainium, I have NDI how to improve that situation.  That puniness is I 
> expect, exactly why RS had to design in some external transistor buffering 
> stages for those 3 signals.  They are in fact very good, 0 loss of rise & 
> fall times going through the buffers, its the puny signals from the gime that 
> are the problem.
> Humm, that said, I also know at one time someone posted to this list several 
> years ago now that allowed as how they could spare about 50 of them, somebody 
> with Williams I believe, did anyone buy up a contingency supply, like Mark? 
> Or GCCC?
> -- 
> Cheers, Gene


The puniness that you so claim may very well have been a major tradeoff that Tandy had to 
make during the design of the GIME chip. The RGB outputs would have had to have 
sufficient current to drive the monitor's impedance of 75 Ohms. That would have more than 
likely required the output to source in the neighborhood of 25 mA as compared to the 1 to 2 
mA based on the schematics and the 2SC945s the chip is driving. Incorpating the large 
NPNs or even larger Lateral PNP transistors in the output would definitely increase area and 

Rise times are effected by load capacitance and source current capabilities of the output 
stage driving that capacitive laod. Fall times are affected by the sink current capabilities of 
the dirver stage and the load capacitance. PCB runners can affect this also. The output stage 
of an IC is designed to source a stated current into a maximum capacitive load. Exceed that 
load capacitance and rise time extends. Simple C dv/dt. The output stage of of an IC is fed 
by a current source that can deliver only so much current.  Fix the current drive and increase 
the load capacitance and rise time will suffer. 

Another thing to consider is that ICs specifications vary across the wafer. An IC in the middle 
of the wafer may have more current drive capability than that of one at the edge of the wafer. 
There are several reasons for this and are really beyond the scope of this reply. Lets just say 
that IC fabrication is not as consistant as one may think, espescially during the mid 80's. With 
4 inch wafers and 1 to 3 micron processes, by today's standard those were the barbarian 
days. If you saw the design process from concept to final product for an IC from the 70s and 
early 80's you would be amazed. The yards of wirewrap on the masive breadboards fefore 
one even committed to silicon was scary. Thank GOD for HDL and computers to simulate the 
design prior to silicon committal. Faster design cycle today than just 20 yrs ago. Now an IC 
can go from concept to final product in less than 6 months. 25 yrs ago it took between 18 and 
24 months. 


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