[Coco] Question re: Cart slot decode
Stephen Castello
zootzoot at cfl.rr.com
Mon Feb 2 19:36:25 EST 2009
On Mon, 2 Feb 2009 18:47:31 -0500 (EST), Steven Hirsch
<snhirsch at gmail.com> had a flock of green cheek conures squawk out:
>I'm looking for a definitive answer on whether accesses between ff60-ff7e
>are supposed to be decoded by the Multi-Pak and/or slot cartridges.
>
>All the docs seem to indicate that the SCS region is ff40-ff5f and the
>control register for the MP is at ff7f. So, who owns the in-between
>addresses?
>
>I have a set of PAL equations for the older (large) MP that suggest it
>listens to the entire ff40-ff7f range, but it would be good to get a
>second opinion :-).
>
>Steve
From a 2001 email. The list doesn't have everything that was made for
the Coco.
------------------------------------------------------------------------------------
FF00: Keyboard row scan
FF01: 0,1 Hsync IRQ control
2 changes FF00 to DDR
7 Hsync flag
FF02: Keyboard column scan
FF03: 0,1 Vsync IRQ control
2 changes FF02 to DDR
7 Vsync flag
$FF1x is a mirror of $FF0x. BUT writing to $FF0x gets the GIME
excited about SAM registers. Writing/reading $FF1x gets you direct
access to the hardware PIA pins, without having the GIME do funny
stuff to your SAM registers. (Alan DeKok)
FF20: 0 Cassette in
1 Bit Bang out
2,7 D/A converter
FF21: 0,1 Carrier FIRQ control
2 changes FF20 to DDR
3 cassette motor
7 carrier detect flag
FF22: 0 Bit Bang in
1 single bit sound out
2 mirror FF02.6
3 RGB monitor flag
4,7 VDG control
FF23: 0,1 Cartridge FIRQ control
2 changes FF22 to DDR
3 sound enable
7 cartridge interrupt flag
The same thing holds true here. $FF3x is a mirror of $FF2x, without
getting the GIME involved. (Alan DeKok)
FF40 \
: > Drive Controller
FF4F /
FF50 \
: > Tandy, Disto mini controller, mirror of drive controller
FF5F /
FF50 \
: > Disto Mini Expansion Bus
FF57 /
FF50 \
: > IDE controller default
FF58 /
The IDE board memory map is as follows:
$FFx0 - 1st 8 bits of DATA register
$FFx1 - Error (read) / Features (Write) register
$FFx2 - Sector count register
$FFx3 - Sector # register
$FFx4 - Cylinder low byte
$FFx5 - Cylinder high byte
$FFx6 - Device/head register
$FFx7 - Status (read) / Command (Write) register
$FFx8 - 2nd 8 bits of DATA register (latch)
Please note, that if you are using ATAPI, most of these change
(which is
why the current driver will not handle ATAPI, except for detecting
it's
presence). (L. Curtis Boyle)
FF60 \ FF60 X position of pen
: > X-pad FF61 Y position of pen
FF63 / FF62 Z pos/pressure of pen
FF63 ???
FF68 \
> RS-232 pak 6551
FF6B /
FF6C \
: > Modem Pak 6551 ACIA
FF6F /
FF70 > alternate address of LR-Tech SASI controller
FF74 > default address of LR-Tech SASI controller
FF70 \
: > IDE controller alternate address
FF78 /
FF7D \
: > Speech/Sound pak FF7E speech chip register
FF7E /
FF7F > Multi-Pak interface slot control switch (0=0,17=1,34=2,51=3)
FF74 \
: > Disto SCII haltless controller additional addresses
FF77 /
FF7A \ FF7A left channel d/a
: > Orchestra 90-CC Pak FF7B right channel d/a
FF7B /
TC^3 SCSI interface uses two addresses anywhere from FF60-FF7F
FF90: 7 CoCo 1/2 compatable map
6 MMU enable
5 IRQ enable
4 FIRQ enable
3 DRAM @ xFExx is constant
2 standard SCS
1,0 ROM control (00=16k int/ext, 10=32k int, 11=32k ext)
FF91: 5 timer select (0=63 microseconds, 1=70 nanoseconds)
0 MMU task select (TR)
According to John "Sockmaster" Kowalski, that 70ns timer input is
really 279ns (=3.579MHz). The 70ns value is either an ordinary typo
or an obsoleted holdover from an earlier never-manufactured design.
The 63.5us source is the 15.75KHz horizontal sweep.
FF92: 5 timer \
4 Horizontal border \
3 Verticle border > IRQ enable
2 Bit Bang in /
1 key press /
0 cartridge /
FF93: 5 timer \
4 Horizontal boarder \
3 Verticle border > FIRQ enable
2 Bit Bang in /
1 key press /
0 cartridge /
FF94: Timer MSN
FF95: Timer LSB
FF98: 7 bit plane
5 burst phase invert
4 monochrome : 000=1 (graphics) 011=8
3 50hz verticle sync / 001=2 (CoCo 1/2) 100=9
2,0 lines per character row < 010=3 110=12
FF99: 6,5 Lines per field (00=192, 01=200, 11=225) \
4,2 Horizontal resolution > video
resolution
1,0 Color resolution /
Due to a design error in the GIME, the "200-line" mode only displays
199 lines of active video on the screen. If you do the BASIC pokes
for 25 lines on the WIDTH 40 and WIDTH 80 screens, you will see the
blinking underscore cursor disappear at the bottom line. If the
graphic screens are poked for 200 lines, the bottom-most line will
be #198, not #199. Try it and see. (Rodney V Hamilton)
FF9A: 5,0 Border color register
FF9C: 3,0 Vertical scroll LSN
FF9D: Vertical offset MSB
FF9E: Vertical offset LSB
FF9F: 7 Virtual horizontal enable
6,0 virtual horizontal offset
FFA0 \
: > MMU @ TR=0
FFA8 /
FFA9 \
: > MMU @ TR=1
FFAF /
FFB0 \
: > Palette registers
FFBF /
FFDF ROM disable \
FFD9 CPU rate \
FFD3 \ \
: > Display offset > SAM emulation echo
FFC7 / /
FFC5 \ /
: > Display mode /
FFC1 / /
FFFE: RESET vector
FFFC: NMI vector
FFFA: SWI1 vector
FFF8: IRQ vector
FFF6: FIRQ vector
FFF4: SWI2 vector
FFF2: SWI3 vector
FFF0: 6309 execption vector (Illegal instruction/division by 0)
--
Stephen
'I had to hit him -- he was starting to make sense.'
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